The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM/RISC-V processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, MIPI, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN, Ethernet, PCIe, UCIe as well as Mixed Signal AMS simulation environment.
Role and Responsibility
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Lead the SOC and Mixed signal verification team and efforts
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Build capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon success is highly desired.
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Develop and signoff on test plans and test cases
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Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces.
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strong knowledge of Verilog, System Verilog, UVM, C/C++
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Experience in usage of assertions, constrained random generation, functional/code coverage
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Knowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows
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Analytical debugging skills
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Excellent team building and management skills
Qualifications and Experience
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BS in EE with 8+ years of experience or MS in EE with 6+ year experience
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Knowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP,
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Knowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI
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Experience managing a verification team
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Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
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Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog
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Experience in writing Test-plans and creating directed and random test cases
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Strong scripting skills in Perl, Python, Linux shells etc.
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Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure
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Strong analytical problem solving and attention to details
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Team player with interest in filing up gaps in product development as needed
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Good written and verbal communication skills
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Good technical documentation skills
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Good interpersonal skills, self-motivated, self-starter
Expectations
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Develop the Test benchses for AMS and FC simulations
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Be UPF Aware.
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Develop the tests to get 95+% coverage for the simulations
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Work with Design team to debug any failures
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Integrate and run the BIST and DFT gate level sims.
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Do code, line and toggle coverage and other metrics.
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Run daily and weekly regressions and publish results
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Responsible for FC RTL, Gate level simulations
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Be a mentor and lead a team of Verification engineers
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Work with Systems and Test engineering team to help validate the parts and release them to production