● Lead the architecture, design, and optimization of high-performance, low-power standard cells targeting advanced process technologies with a strong focus on Performance, Power, and Area (PPA).
● Design and optimize transistor-level circuits including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, arithmetic cells, and other complex sequential and combinational logic.
● Architect and develop advanced arithmetic building blocks, including adders, multipliers, integer and floating-point MAC units, for high-performance compute applications.
● Develop schematics using Cadence Virtuoso and perform post-layout validation through parasitic extraction using StarRC or Quantus.
● Perform circuit verification across all PVT corners using HSPICE, PrimeSim XA, or Spectre, ensuring robust functionality, timing, and power performance.
● Drive statistical verification using Monte Carlo methodologies and advanced variation analysis with Solido, Spectre FMC, or equivalent tools.
● Own reliability sign-off activities, including electromigration (EM), IR-drop, self-heating, BTI/HCI aging analysis, while ensuring ESD and latch-up robustness.
● Drive low-power circuit innovations through multi-Vt optimization, leakage reduction, power gating, retention strategies, isolation cells, and power-intent-aware design methodologies.
● Collaborate closely with custom layout teams to optimize layouts for Layout Dependent Effects (LDE), manufacturability, coloring compliance, matching, and pin accessibility.
● Partner with Characterization, Physical Design, STA, CAD, and Product Engineering teams to ensure successful library development, silicon readiness, and production-quality deliverables.
● Drive design methodology improvements, automation initiatives, and technical best practices across the circuit design organization.
● Mentor engineers and provide technical leadership in circuit design, methodology development, and advanced technology enablement.