DFT Engineer
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Before you apply
LocationIND-Bangalore Electronic City - S1
Work modeon-site
Typefull-time
SenioritySenior
Experience6+ yrs
Company size10,000+ people
PostedOct 28, 2026 · 1w ago
Verified live3d ago
At a glanceSummarised by Seekless from the posting.
Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience
Required experience in silicon bring-up and yield improvement
Solid understanding of DFT techniques
Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process
Experience in MBIST architecture and insertion
Experience in analyzing and debugging simulation failures
Solid understanding of digital logic fundamentals
Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite
Proficiency with Perl or other scripting languages
Strong communication and interpersonal skills
Experience in STA constraint development in DFT modes
Equal opportunity employer statement
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence
Skills
Mentor Tessent
Synopsys DFT
Perl
ATE
MBIST
ATPG
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Job Description:
As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
Key Responsibilities:
•
Work closely with the ATE engineer on yield improvement and analysis.
•
Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
•
Participate in block and chip-level DFT implementation, developing and executing all related tasks.
•
Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
•
Perform ATPG and pattern simulation for both MBIST and scan.
•
Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
•
Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.
Required Qualifications:
•
Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience
•
Required experience in silicon bring-up and yield improvement.
•
Solid understanding of DFT techniques.
•
Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
•
Experience in MBIST architecture and insertion.
•
Experience in analyzing and debugging simulation failures.
•
Solid understanding of digital logic fundamentals.
•
Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
•
Proficiency with Perl or other scripting languages.
•
Strong communication and interpersonal skills.
•
Plus: Experience in STA constraint development in DFT modes
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.