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Lumilens

Senior Silicon Photonics Engineer

LocationSingapore
Work modeon-site
Typefull-time
DepartmentEngineering
Company size51+ people
First seen1mo ago
Last seen2d ago
Role Overview
You will design high-speed silicon photonic integrated circuits operating at the limits of bandwidth and integration, and take them from concept → tapeout → silicon validation.
This role is suitable for strong PhD graduates through early-career engineers (~0–5 years experience) who want to work on real, production-bound systems, not just simulations.
Roles & Responsibilities
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Design and optimize silicon photonic devices and circuits, including:
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High-speed modulators (MZI, ring, advanced structures)
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Photodetectors and receiver building blocks
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Passive components (couplers, filters, routing)
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Perform multi-domain simulations (EM, circuit, thermal) to meet targets in:
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Bandwidth (200G/lane+)
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Insertion loss, extinction ratio, efficiency
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Implement PIC layouts (GDS) using foundry PDKs and support tapeouts
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Co-design with electronics and packaging teams for CPO/NPO systems:
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RF effects, parasitics, signal integrity, and thermal constraints
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Support silicon bring-up and characterization:
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Correlate measurement vs simulation
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Drive design iterations and improvements
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Contribute to design libraries, modeling, and methodology development
Requirements
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Education
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PhD in Electrical Engineering, Physics, or related field (silicon photonics or closely related area)
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Experience
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0–5 years of relevant experience (including fresh PhD graduates)
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Technical Skills
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Experience in design and simulation of silicon photonic devices or PICs
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Strong understanding of guided-wave optics and device physics
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Familiarity with tools such as Lumerical, COMSOL, or equivalent
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Implementation Skills
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Exposure to PIC layout and tapeout flows (PDK, DRC/LVS)
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System Awareness
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Basic understanding of optical communication systems and/or RF effects
Nice to Have
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Experience with high-speed devices (>100 GHz bandwidth or equivalent)
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Exposure to CPO/NPO or optical transceiver architectures
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Familiarity with SiPh + III-V integration
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Experience with inverse design / adjoint methods (e.g., Meep)
Why Join Us
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Work on real products at 200G/lane+, not just research prototypes
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Direct impact on AI infrastructure and hyperscale systems
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Fast iteration cycles from design → silicon → system
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High ownership early in your career
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Comprehensive benefits package including health insurance
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Collaborative environment with world-class engineering and R&D teams
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