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VO
Volantis Semiconductor, Inc.
PHY/SERDES Lead
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Salary
No pay range posted
Location
Remote, Hybrid Remote/SF Bay Area/Austin/Boston
Also in
San Francisco Bay Area
Work mode
hybrid
Type
full-time
Seniority
Lead
Department
PHY/SERDES
Company size
201–500 people
Posted
Jul 28, 2026 · 2mo ago
Verified live
2h ago
California and Massachusetts laws require most employers to post a pay range.
At a glance
Summarised by Seekless from the posting.
Must have
5
Multiple successful tapeouts of SERDES or PHY macros
Deep understanding of tradeoffs between XSR/VSR/LR class SERDES and different operating regimes and challenges
Understanding and ownership of end to end link definition and architecture
Experience with bringup of PHYs
Understanding of the integration of PHYs into the system level
Nice to have
4
Deep knowledge of and hands-on with chiplet interfaces like UCIe or BoW
Deep knowledge and hands-on execution of optical interconnect PHY layers
Knowledge of re-driven and re-timed PHY interfaces
Experience with customization of PHYs
Skills
SERDES
PHY
UCIe
BoW
optical interconnect
What We’re Looking For:
We’re looking for a PHY/SERDES Lead to own and lead the development of our semi-custom optical PHY layer.
Ideal Background:
•
Multiple successful tapeouts of SERDES or PHY macros (not necessarily only chiplet interfaces, SERDES also counts here)
•
Deep understanding of tradeoffs between XSR/VSR/LR class SERDES and different operating regimes and challenges
•
Understanding and ownership of end to end link definition and architecture
•
Experience with bringup of PHYs
•
Understanding of the integration of PHYs into the system level
Strongly Preferred:
•
Deep knowledge of and hands-on with chiplet interfaces like UCIe or BoW
•
Deep knowledge and hands-on execution of optical interconnect PHY layers
•
Knowledge of re-driven and re-timed PHY interfaces
•
Experience with customization of PHYs
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