Staff Layout Engineer
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Before you apply
LocationSingapore-Yishun
Work modeon-site
SeniorityLead
Experience8+ yrs
Company size10,000+ people
PostedOct 12, 2026 · 3w ago
Verified live5d ago
At a glanceSummarised by Seekless from the posting.
Strong layout knowledge with a minimum of 8 years of experience
Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools
Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm, 2nm, A14 and below
Experienced in digital (standard cell, memory, I/O) layout
Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes
Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools
Good experience in Floor-planning, hierarchy layout and chip integration
Able to lead or train a team of junior engineers
Good knowledge of memory layout topology
Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines
Self-reliant, with the ability to work independently as well as in a team
Good leadership quality in project management
Experienced in analog layout is also a plus
Experience in memory compiler will be a plus
Knowledge of Script Programming and SKILL Programming would be a plus
Must be available to re-locate to Singapore immediately
Skills
Cadence
Virtuoso
CALIBRE
Hercules
LVS
DRC
ERC
Antenna
Electro Migration
SKILL Programming
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Job Description:
Staff Layout Engineer
Job descriptions and the level of expertise:
The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.
In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.
Requirements:
IC Layout
Strong layout knowledge with a minimum of 8 years of experience
Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm,2nm ,A14 and below
Experienced in digital (standard cell, memory, I/O) layout
Experienced in analog layout is also a plus
Job description:
IC Layout
Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
Schedule time-line & layout floor-planning
Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
Skill Set (Mem)
•
Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
•
Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
•
Good experience in Floor-planning, hierarchy layout and chip integration.
•
Experience in memory compiler will be a plus.
•
Knowledge of Script Programming and SKILL Programming would be a plus.
•
Able to lead or train a team of junior engineers
•
Good knowledge of memory layout topology.
•
Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
•
Self-reliant, with the ability to work independently as well as in a team.
•
Good leadership quality in project management.
Re-location
•
Must be available to re-locate to Singapore immediately.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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