LocationAZ - Chandler; CA - San Jose - 3870 N. First St; CA - San Jose - 3850 N. First St; CA - Roseville; TX - Austin - Park Centre
Work modeon-site
Typefull-time
SeniorityLead
Experience12+ yrs
EquityIncluded
Company size10,000+ people
First seenOct 3, 2026 · 1w ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Must have15
12.5+ years in functional verification of complex SoC designs
Expertise in System Verilog, UVM, formal verification methodologies
Proven experience in methodology development and tool automation
Familiarity with AI/ML-driven EDA tools and scripting for flow integration
Good understanding of SoC architectures – ARM/RISC-V
Expertise in at least two of the following domains/peripherals: CPU subsystems, PCIe Gen3/Gen4/Gen5, DDR4/DDR5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB, Security and cryptography IPs
Exposure to emulation, hardware prototyping and post-silicon debug
Experience with FPGA-based acceleration platforms and simulation/emulation flows
Software & Scripting: Python, TCL/TK, and C/C++ for automation and validation
Familiarity with Siemens/Cadence/Synopsys verification suites
Familiarity with revision control systems (Git, Perforce, svn)
Excellent debug skills
Experience working with global cross functional teams
Excellent communication and collaboration skills
BS or MS in Electrical/Electronic Engineering with 12+ years of experience
Nice to have4
Strong understanding of FPGA architecture
Experience with coverage-driven verification using ML-based optimizations
Experience in emulation, hardware prototyping and post-silicon debug
Knowledge and exposure to complete SOC RTL to GDS to silicon release flow
Skills
System Verilog
UVM
AI/ML
EDA tools
ARM
RISC-V
PCIe Gen3/Gen4/Gen5
DDR4/DDR5
LPDDR4X
MIPI DSI/CSI
Ethernet MAC
USB
Security and cryptography IPs
Python
TCL/TK
C/C++
Git
Perforce
svn
Siemens/Cadence/Synopsys verification suites
FPGA
Benefits
Competitive base pay
Restricted stock units
Quarterly bonus payments
Health insurance
Retirement savings plans
ESPP program
About the company
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
The FPGA Business Unit of Microchip Technology Inc is seeking an experienced and innovative verification engineer for our team in Chandler, Arizona to work on the verification of our next generation, highly secure, low-power FPGA device products.
Key Responsibilities:
•
Verification of complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.
•
Develop and maintain highly reusable UVM based test benches and verification environments.
•
Involve in RTL, power aware and gate level verification.
•
Contribute to quality and productivity be using AI/ML-enabled verification methodologies
•
Collaborate with emulation and hardware prototyping teams to define a unified verification methodology.
•
Collaborate with architecture and design teams to ensure seamless execution and first-silicon success.
•
Mentor junior team members.
Requirements/Qualifications:
Required Qualifications:
•
12.5+ years in functional verification of complex SoC designs
•
Expertise in System Verilog, UVM, formal verification methodologies
•
Proven experience in methodology development and tool automation.
•
Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
•
Good understanding of SoC architectures – ARM/RISC-V
•
Expertise in at least two of the following domains/peripherals
•
CPU subsystems
•
PCIe Gen3/Gen4/Gen5
•
DDR4/DDR5, LPDDR4X
•
MIPI DSI/CSI
•
Ethernet MAC
•
USB
•
Security and cryptography IPs.
•
Exposure to emulation, hardware prototyping and post-silicon debug
•
Experience with FPGA-based acceleration platforms and simulation/emulation flows.
•
Software & Scripting:
•
Python, TCL/TK, and C/C++ for automation and validation.
•
Tools:
•
Familiarity with Siemens/Cadence/Synopsys verification suites
•
Revision control systems (Git, Perforce, svn).
•
Excellent debug skills
•
Experience working with global cross functional teams
•
Excellent communication and collaboration skills
Preferred Skills:
•
Highly Desirable: Strong understanding of FPGA architecture
•
Experience with coverage-driven verification using ML-based optimizations.
•
Experience in emulation, hardware prototyping and post-silicon debug,
•
Knowledge and exposure to complete SOC RTL to GDS to silicon release flow.
Required Education:
•
BS or MS in Electrical/Electronic Engineering with 12+ years of experience
Travel Time:
0% - 25%
Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
80% sitting, 10% walking, 10% standing
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.*
*Range is dependent on numerous factors including job location, skills and experience.
Legal
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.