● Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, VLSI, or a related discipline.
● Experience with advanced-node ASIC/SoC designs and high-volume production silicon.
● Experience with AI accelerators, high-performance compute, CPU, GPU, NoC, memory subsystem, or complex SoC architectures.
● Familiarity with automotive or functional safety standards such as ISO 26262 is preferred.
● Experience developing DFT methodologies for low-power designs, including UPF-aware test strategies, power domain testing, isolation, retention, and test-mode power management.
● Good understanding of Static Timing Analysis, test-mode constraints, scan timing, OCC, clocking, reset architecture, and multi-mode test closure.
● Experience with silicon bring-up, ATE pattern deployment, production test debug, yield ramp, and manufacturing quality improvement.
● Experience building automation using Tcl, Python, Perl, or other scripting languages.
● Track record of leading technical initiatives, mentoring engineering teams, and driving methodology improvements.
● Experience with sub-5nm or leading-edge technology nodes.
● Experience with automotive-grade silicon quality, reliability requirements, or ISO 26262-compliant development flows.
● Knowledge of advanced test methodologies including cell-aware test, timing-aware ATPG, hierarchical DFT, streaming scan networks, and adaptive test.
● Experience with memory repair, redundancy analysis, fuse flows, and production repair strategies.
● Familiarity with ATE platforms, test program development, pattern conversion, and tester correlation.
● Exposure to silicon lifecycle management, in-system test, on-chip monitors, and field diagnostics.
● Experience with security-aware test, debug access control, or secure JTAG methodologies.
● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.
● Passion for building robust, high-quality silicon and driving test innovation under aggressive product schedules.
● Background in DFT architecture and methodology for complex ASIC/SoC designs; scan insertion, scan compression, ATPG, MBIST, LBIST, JTAG, boundary scan, and IJTAG; AI compute, processor, GPU, accelerator, networking, or high-performance SoC test; fault simulation, coverage closure, pattern generation, and diagnosis; post-silicon debug, yield improvement, silicon correlation, and production test support; low-power and advanced-node DFT implementation; DFT verification, test-mode validation, and sign-off; cross-functional silicon development with RTL, verification, physical design, STA, validation, and manufacturing teams; or DFT tool flow development, automation, and methodology improvement.