● Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs.
● Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence to zero or signoff-acceptable violations.
● Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity, device-recognition, hierarchy, and advanced-node rule issues.
● Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to closure.
● Perform hands-on physical implementation and ECO changes, including routing and via edits, metal-shape modifications, cell movement, filler/decap/endcap updates, power-grid modifications, and other layout changes required for signoff.
● Define, customize, and enhance PERC and reliability verification flows covering ESD, EOS, latch-up, point-to-point resistance, current-density constraints, and high-current paths.
● Develop Tcl and Python/Perl/Unix shell automation for violation analysis, implementation database queries, physical ECOs, PV execution, and signoff reporting.
● Drive PV closure for advanced FinFET and GAA technologies, including restrictive spacing, coloring, cut-mask, EUV/multi-patterning, and other advanced-node-specific requirements.
● Influence floorplanning, power-grid planning, and implementation methodology from a physical verification perspective to minimize downstream iterations and late-stage signoff violations.
● Support hierarchical and full-chip PV methodologies for digital-on-top, mixed-signal, and multi-voltage SoCs, including IP integration and boundary/interface verification.
● Partner with Physical Design, STA, Power Integrity, Analog, and Reliability teams to ensure PV-driven changes preserve timing, congestion, routability, signal integrity, power integrity, reliability, and design functionality.
● Develop and optimize physical verification flows for runtime, scalability, robustness, and ease of use across block and full-chip designs.
● Partner with CAD teams, foundries, and EDA vendors to qualify technology nodes and rule decks, resolve complex PV/reliability issues, and improve verification and signoff methodologies.
● Drive density, metal-fill, DFM/DFY, and pattern-matching verification while ensuring associated changes do not introduce timing, reliability, or physical verification regressions.
● Mentor engineers on physical verification methodology, advanced-node debugging, root-cause analysis, implementation fixes, and tape-out signoff best practices.