FPGA Engineer
Read straight from Northrop Grumman's careers page, verified 2d ago.Seekless can tailor your résumé to it.
Seekless can write your résumé for this posting first.
Before you apply
Salary$96k – $145k
LocationUnited States-Illinois-Rolling Meadows
Work modeon-site
Typefull-time
SeniorityMid
Experience2+ yrs
Company size10,000+ people
PostedNov 2, 2026 · 3d ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline and minimum 2 years of relevant FPGA/ASIC design experience or master's degree with relevant experience
Solid understanding of VHDL, Verilog, or SystemVerilog for RTL design and verification
Experience developing synchronous RTL, including state machines, control logic, data paths, clocks, and resets
Experience developing or modifying RTL testbenches and debugging simulation failures
Familiarity with the overall FPGA development flow, including RTL simulation, synthesis, place and route, timing analysis, and generation of FPGA programming files
Experience with at least one major FPGA device architecture and its associated development toolchain, such as AMD Xilinx devices with Vivado or Intel FPGA devices with Quartus
Experience with FPGA electronic design automation tools, such as ModelSim/QuestaSim, Synplify, Vivado, Quartus, SOPC Builder/Qsys/Platform Designer, or DSP Builder
Experience with scripting or high-level programming languages, such as MATLAB, Python, or C/C++
Exposure to developing engineering requirements, design specifications, test specifications, or other controlled technical documentation
Ability to complete defined technical assignments with moderate guidance, communicate technical status and blockers proactively, incorporate peer-review feedback, and work effectively across engineering disciplines
Must have interim secret clearance prior to starting. Once started, must have the ability to obtain and maintain a secret security clearance
Current or active Secret or Top Secret clearance with SCI/SAP eligibility
Academic or practical experience with RF, EO/IR, communications, or digital signal-processing concepts, including I/Q representation, sampling, filtering, or frequency-domain analysis
Experience implementing digital signal-processing or image-processing functions in FPGA logic
Experience with high-speed interfaces such as AXI, PCIe, Aurora, JESD, or 10G/25G/40G+ Ethernet
Experience developing and integrating FPGA/software interfaces, register maps, and controls
Experience with MATLAB or Simulink for algorithm modeling, simulation, or FPGA implementation support
Familiarity with clock-domain crossings, reset-domain crossings, and timing constraints
Experience integrating or testing FPGA designs in a laboratory environment using signal generators, logic analyzers, digital oscilloscopes, protocol analyzers, or embedded FPGA debug tools such as Vivado ILA or Intel SignalTap
Experience using SystemVerilog/UVM, cocotb, or other structured verification frameworks
Familiarity with configuration-management, requirements, planning, and review tools such as Git, SVN, ClearCase, DOORS, Jira, Rally, or ClearQuest
Strong communication and teamwork skills, with the ability to work independently on defined assignments, seek feedback, and apply feedback to improve technical work
Strong sense of ownership and responsibility for technical deliverables
Demonstrated adaptability, creativity, collaboration, and initiative, with enthusiasm for solving challenging problems and contributing to the advancement of technologies
U.S. citizenship
Skills
VHDL
Verilog
SystemVerilog
AMD Xilinx Vivado
Intel Quartus
ModelSim
QuestaSim
Synplify
MATLAB
Python
C/C++
Git
SVN
ClearCase
DOORS
Jira
Rally
ClearQuest
SystemVerilog/UVM
cocotb
PCIe
AXI
Aurora
JESD
Ethernet
Simulink
Benefits
Health insurance
Life insurance
Disability insurance
Savings plan
Paid holidays
Paid time off
Bonus
RELOCATION ASSISTANCE: Relocation assistance may be availableCLEARANCE REQUIRED FOR START: YesCLEARANCE TYPE: SecretTRAVEL: Yes, 10% of the Time
Description
About the company
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation’s history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they’re making history.
We are seeking talented FPGA Design Engineers to join our growing team in Rolling Meadows, Illinois.
The Multidomain Sensing, Targeting, and Survivability Division (MSTS), located in the Northwest Chicago suburbs, develops operational Electronic Warfare (EW) and targeting systems that provide situational awareness, self-protection, and offensive electronic attack capability to platforms across the spectrum from visible light IR to millimeter wave RF. By joining us, you’ll work on projects that help safeguard our nation related to land forces, rotary wing survivability systems, international and U.S. military electronic warfare systems, communications systems, missile warning systems and sensors, infrared counter-measure systems (IRCM), automatic test equipment, modeling and simulation, and situational awareness programs.
Responsibilities
As an FPGA Design Engineer, you will join a diverse, high-performing team responsible for the end-to-end development of advanced RF and EO/IR products. You will contribute across the FPGA development lifecycle, including requirements analysis and refinement, system and FPGA architecture, RTL design and coding, testbench development, verification, synthesis, implementation, timing closure, hardware integration, qualification, production support, and troubleshooting.
You will develop FPGA-based digital subsystems integrated into circuit card assemblies, working closely with systems, software, hardware, and integration & test engineers. Designs utilize FPGA technologies from major vendors including AMD Xilinx, Intel, and support high-speed interfaces, RF and EO/IR signal-processing chains, controls, data links, embedded processing, and processor interfaces.
This position will be full-time and on-site at our Rolling Meadows, IL. location.
Requirements
The qualifications for the FPGA Design Engineer are below.
Basic Qualifications for FPGA Design Engineer
•
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with a minimum of 2 years of relevant FPGA/ASIC design experience; or a master’s degree with relevant experience.
•
Solid understanding of VHDL, Verilog, or SystemVerilog for RTL design and verification.
•
Experience developing synchronous RTL, including state machines, control logic, data paths, clocks, and resets.
•
Experience developing or modifying RTL testbenches and debugging simulation failures.
•
Familiarity with the overall FPGA development flow, including RTL simulation, synthesis, place and route, timing analysis, and generation of FPGA programming files.
•
Experience with at least one major FPGA device architecture and its associated development toolchain, such as AMD Xilinx devices with Vivado or Intel FPGA devices with Quartus.
•
Experience with FPGA electronic design automation tools, such as ModelSim/QuestaSim, Synplify, Vivado, Quartus, SOPC Builder/Qsys/Platform Designer, or DSP Builder.
•
Experience with scripting or high-level programming languages, such as MATLAB, Python, or C/C++.
•
Exposure to developing engineering requirements, design specifications, test specifications, or other controlled technical documentation.
•
Ability to complete defined technical assignments with moderate guidance, communicate technical status and blockers proactively, incorporate peer-review feedback, and work effectively across engineering disciplines.
•
U.S. citizenship.
•
Must have interim secret clearance prior to starting. Once started, must have the ability to obtain and maintain a secret security clearance.
Preferred Qualifications
•
Current or active Secret or Top Secret clearance with SCI/SAP eligibility.
•
Academic or practical experience with RF, EO/IR, communications, or digital signal-processing concepts, including I/Q representation, sampling, filtering, or frequency-domain analysis.
•
Experience implementing digital signal-processing or image-processing functions in FPGA logic.
•
Experience with high-speed interfaces such as AXI, PCIe, Aurora, JESD, or 10G/25G/40G+ Ethernet.
•
Experience developing and integrating FPGA/software interfaces, register maps, and controls.
•
Experience with MATLAB or Simulink for algorithm modeling, simulation, or FPGA implementation support.
•
Familiarity with clock-domain crossings, reset-domain crossings, and timing constraints.
•
Experience integrating or testing FPGA designs in a laboratory environment using signal generators, logic analyzers, digital oscilloscopes, protocol analyzers, or embedded FPGA debug tools such as Vivado ILA or Intel SignalTap.
•
Experience using SystemVerilog/UVM, cocotb, or other structured verification frameworks.
•
Familiarity with configuration-management, requirements, planning, and review tools such as Git, SVN, ClearCase, DOORS, Jira, Rally, or ClearQuest.
•
Strong communication and teamwork skills, with the ability to work independently on defined assignments, seek feedback, and apply feedback to improve technical work.
•
Strong sense of ownership and responsibility for technical deliverables.
•
Demonstrated adaptability, creativity, collaboration, and initiative, with enthusiasm for solving challenging problems and contributing to the advancement of technologies.
Benefits
Primary Level Salary Range: $96,300.00 - $144,500.00The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate’s experience, education, skills and current market conditions.Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.