* Develop and implement efficient and comprehensive verification environments and test benches using industry-standard methodologies (e.g., UVM, SystemVerilog).
* Create detailed verification plans based on design specifications, identifying key functionalities and potential corner cases.
* Develop, execute, and debug test cases to thoroughly verify the design against its specifications.
* Analyze simulation results, identify discrepancies, and work closely with design engineers to resolve issues.
* Develop and maintain verification collateral, including assertions, functional coverage models, and verification scripts.
* Participate in verification reviews, contributing to the improvement of verification methodologies and processes.
* Collaborate with design, architecture, and software teams throughout the product development lifecycle.
* Contribute to the continuous improvement of verification flows and tools.
* Document verification strategies, test plans, and results effectively.