· Drive a “zero-defect” mindset across the verification team
· Provide technical leadership and guidance on complex verification challenges
· Mentor and grow a small team of engineers
· Define and execute verification plans
· Develop and implement verification testbenches
· Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs
· Develop directed and constrained-random stimulus
· Analyze RTL, functional coverage, and assertion coverage results
· Define and develop functional coverage models
· Develop and maintain SystemVerilog assertions (SVA)
· Apply formal verification methodologies
· Demonstrate strong debugging skills, including failure reproduction and root-cause analysis
· Exhibit strong analytical and problem-solving skills; familiarity with major simulation and debug tools is a plus