Lead STA Engineer
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Before you apply
LocationBangalore
Typefull-time
SeniorityLead
Experience7+ yrs
Company size10,000+ people
PostedSep 25, 2026 · 1mo ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
Master's degree or Bachelor's degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.
7+ years of hands-on experience in static timing analysis for complex ASIC/SoC designs.
Experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes
Proven experience leading STA efforts for multiple successful tape-outs.
Expertise in industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
Strong understanding of digital design fundamentals, clocking architectures, and low-power techniques
In-depth knowledge of timing constraints (SDC) and their application.
Proficiency in scripting languages such as Perl, Python, or TCL.
Strong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.
Work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities
Should be able to do IP level synthesis.
Drive a small team of STA engineers.
Skills
Synopsys PrimeTime
Cadence Tempus
Perl
Python
TCL
SDC
About the role
Summary: Seeking a highly skilled and experienced Lead STA Engineer to lead and execute static timing analysis for complex semiconductor designs, ensuring timing closure and performance targets are met. This role involves guiding a team, developing methodologies, and collaborating with design and verification teams to deliver high-quality products.
Job Qualification:
•
Master’s degree or Bachelor’s degree in Electronics/ Electrical Engineering, Computer Engineering, or a related field.
•
7+ years of hands-on experience in static timing analysis for complex ASIC/SoC designs.
•
Experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes
•
Proven experience leading STA efforts for multiple successful tape-outs.
•
Expertise in industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).
•
Strong understanding of digital design fundamentals, clocking architectures, and low-power techniques
•
In-depth knowledge of timing constraints (SDC) and their application.
•
Proficiency in scripting languages such as Perl, Python, or TCL.
•
Strong communication and interpersonal skills, with the ability to collaborate effectively in a global team environment.
•
Work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities
Key Responsibilities
•
Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.
•
Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.
•
Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).
•
Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).
•
Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.
•
Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.
•
Drive a small team of STA engineers.
•
Should be able to do IP level synthesis.
About the company
More information about NXP in India…