We are seeking a skilled DFT Engineer to lead DFT architecture and methodology development for complex test‑chip designs. The role involves defining and implementing Scan, MBIST, ATPG, and supporting post‑silicon debug activities. The engineer will collaborate with design, verification, and physical design teams to ensure seamless BIST integration and validation. Strong hands‑on experience in JTAG, Memory BIST, ATPG, SystemVerilog, and UVM is essential, along with proficiency in simulation, testbench development, and ATE pattern handling. Expertise in scripting with Tcl, Python, and Shell is required. Experience in RTL development and functional verification is a plus