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Astera Labs

Principal Architect

LocationHaifa, Tel Aviv, Tel Aviv-Yafo, Tel Aviv District, Israel
Work modeon-site
Typefull-time
DepartmentArchitecture CCE2
Company size1,001–5,000 people
First seen1w ago
Last seen2d ago
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the role
We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.
This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.
Key Responsibilities
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Define and drive system and chip-level architecture for high-speed connectivity products
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Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems
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Analyze system requirements and translate them into scalable and efficient hardware architectures
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Drive tradeoff analysis across performance, power, latency, area, and cost
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Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering
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Define and review micro-architecture specifications and ensure alignment across teams
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Contribute to standard-based and custom protocols for next-generation AI infrastructure
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Support performance modeling, simulation, and architectural validation
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Work closely with customers and partners to understand emerging use cases and requirements
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Mentor engineers and help build strong technical leadership within the Israel R&D center
Basic Qualifications
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10+ years of experience in semiconductor architecture, ASIC design, or system engineering
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Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem
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Deep understanding of Networking and Ethernet (e.g., 25G/50G/100G/400G and beyond)
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Experience designing high-speed, low-latency data paths
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Solid understanding of SoC architecture and integration challenges
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Experience working across full chip development lifecycle
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Strong analytical and problem-solving skills with ability to evaluate complex tradeoffs
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Ability to influence and collaborate across multiple engineering domains
Preferred Experience
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Experience with CXL, NVLink, UALink, or other advanced interconnect protocols
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Background in AI/ML infrastructure, data center systems, or hyperscaler environments
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Experience with SerDes-based systems and high-speed PHY integration
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Familiarity with networking stacks, switching, or RDMA technologies
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Experience with performance modeling tools and architectural simulators
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Knowledge of power/performance optimization techniques at system level
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Track record of driving architecture from concept to silicon
Legal
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
More roles at Astera Labs
Tech Lead PCB Layout EngineerTemplate JobSenior System Validation EngineerManager, Digital DesignLead Logic Design - PCIE IP/Subsystem Engineer
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