Digital Design Engineer
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Before you apply
LocationEgypt
Typefull-time
SeniorityEntry
Experience1+ yrs
EquityIncluded
Company size10,000+ people
PostedNov 3, 2026 · 2d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
1+ years of experience in digital RTL design using SystemVerilog/Verilog
Solid understanding of digital design fundamentals: synchronous design, CDC, FSMs, pipelining, and low-power techniques
Hands-on experience with industry EDA tools (synthesis, lint, CDC, simulation)
Familiarity with scripting (Python, TCL, Perl) for design automation
Strong problem-solving skills and ability to work in a cross-functional team
Experience with high-speed serial interfaces (SerDes, PCIe, Ethernet, CXL) or optical link control
Exposure to silicon photonics, co-packaged optics, or advanced packaging products
Experience with ARM-based SoC integration, AMBA protocols (AXI/AHB/APB), and standard IP integration flows
Prior tape-out experience on advanced process nodes
Knowledge of UPF/low-power flows and DFT (scan, MBIST, boundary scan)
Skills
SystemVerilog
Verilog
UVM
Python
TCL
Perl
SerDes
PCIe
Ethernet
CXL
ARM
AMBA
AXI
AHB
APB
Benefits
Base salary
Equity
Annual bonus
Medical insurance
Title: Digital Design Engineer
About GF
GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power efficient and high-performance solutions for high growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com.
Responsibilities
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Develop, document, and maintain RTL (SystemVerilog/Verilog) for digital subsystems within the CPO product, including control logic, register interfaces, link management, and DFT structures.
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Collaborate with architecture, analog/mixed-signal, and photonics teams to define digital interfaces and control schemes for co-packaged optical modules.
•
Own micro-architecture specifications, design reviews, and integration of digital IP into the top-level SoC.
•
Drive synthesis, timing closure, CDC, lint, and low-power (UPF) sign-off in coordination with the physical design team.
•
Perform FPGA prototyping and testing of digital subsystems to validate functionality, accelerate pre-silicon software bring-up, and de-risk RTL ahead of tape-out.
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Develop and execute UVM-based testing, including building reusable verification components, writing constrained-random tests, and driving functional and code coverage closure.
•
Support verification efforts by collaborating with the DV team on testbench development, coverage closure, and debug.
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Participate in tape-out readiness activities, including ECO planning, gate-level simulation, and post-silicon bring-up support.
•
Contribute to design methodology, reuse strategy, and quality improvements across the team.
Required Qualifications
•
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
•
1+ years of experience in digital RTL design using SystemVerilog/Verilog.
•
Solid understanding of digital design fundamentals: synchronous design, CDC, FSMs, pipelining, and low-power techniques.
•
Hands-on experience with industry EDA tools (synthesis, lint, CDC, simulation).
•
Familiarity with scripting (Python, TCL, Perl) for design automation.
•
Strong problem-solving skills and ability to work in a cross-functional team.
Preferred Qualifications
•
Experience with high-speed serial interfaces (SerDes, PCIe, Ethernet, CXL) or optical link control.
•
Exposure to silicon photonics, co-packaged optics, or advanced packaging products.
•
Experience with ARM-based SoC integration, AMBA protocols (AXI/AHB/APB), and standard IP integration flows.
•
Prior tape-out experience on advanced process nodes.
•
Knowledge of UPF/low-power flows and DFT (scan, MBIST, boundary scan).
We Offer
•
Base Salary
•
Equity
•
Annual Bonus Plan
•
Medical Insurance
Legal
GlobalFoundries is committed to equal employment opportunity and maintaining a workplace free from discrimination and harassment. Employment decisions are based on legitimate, job-related criteria, including qualifications, skills, experience, performance, and business needs, and are made without regard to any characteristic protected by applicable law.
All employment policies and practices, including recruitment, selection, training, development, promotion, compensation, benefits, and termination, without regard to age, ancestry, color, disability, marital status, national origin, race, religion, sex, veteran status, or any other characteristic protected by applicable law.
No Recruitment Fee Policy: GlobalFoundries is committed to ethical and transparent hiring practices. Candidates will not be charged any fees at any stage of the recruitment process. Any request for payment related to a GlobalFoundries employment opportunity is unauthorized and should be reported immediately. All legitimate recruitment communications are conducted exclusively through official GlobalFoundries channels. To report concerns or suspected recruitment fraud, please contact our Ethics & Compliance Office at global[dot]compliance[at]globalfoundries[dot]com or visit our official website.
The Ethics & Compliance mailbox is not a recruitment channel. CVs/resumes submitted to this mailbox will not be reviewed, processed, or considered for employment opportunities. Please apply through the official GlobalFoundries careers site only.
Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/