Staff Digital Verification Engineer
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Before you apply
Salary$160k – $210k
LocationAustin, TX, Pittsburgh, PA, San Francisco, Bay Area, San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Typefull-time
SeniorityLead
Experience10+ yrs
DepartmentVerification & Emulation
EquityIncluded
Company size51–200 people
PostedSep 1, 2026 · 2mo ago
Verified live3d ago
At a glanceSummarised by Seekless from the posting.
Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout
Expertise in UVM-based testbench architecture and constrained-random verification methodology
C/C++ experience for modelling or verification
Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs
Proven ability to debug complex simulation failures
Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development
Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership
Experience in Formal verification (JasperGold or similar)
Experience building or using AI Agentic flows for DV
Software/Firmware based testing experience and working with software teams pre-silicon
Post-silicon experience
Understanding and experience in SoC Architecture: processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals
Power aware verification and UPF
Skills
UVM
SystemVerilog
C
C++
Python
JasperGold
ARM
RISC-V
AMBA AXI
AMBA ACE
AMBA CHI
UPF
Benefits
401(k) match
Paid parental leave
Equity
About the company
Efficient Computer is rethinking computing from the ground up to solve one of AI’s biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we’re accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it’s needed and help shape the next generation of computing.
About the role
We are looking for an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Requirements
Required Qualifications & Experience
•
Education: Bachelor’s or Master’s/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
•
Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
•
UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
•
C/C++ experience for modelling or verification.
•
Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
•
Debug Skills: Proven ability to debug complex simulation failures.
•
Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
•
Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.
Nice to have
Ways to stand out :
•
Experience in Formal verification (JasperGold or similar).
•
Experience building or using AI Agentic flows for DV.
•
Software/Firmware based testing experience and working with software teams pre-silicon
•
Post-silicon experience
•
SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
•
Power aware verification and UPF
Benefits
We offer a competitive base salary for this role, generally ranging from $160,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
Why Join Efficient?
Build what’s next. At Efficient, you’ll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.