Principal Layout Engineer
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Before you apply
Salary€61k – €84k
LocationCatania
Work modeon-site
Typefull-time
SeniorityLead
Experience10+ yrs
DepartmentSmart Analog Interfaces
EquityIncluded
Company size10,000+ people
PostedSep 21, 2026 · 1mo ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
BSEE or MSEE
10+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS
Expert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC
Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices
Proven experience leading analog-on-top and digital-on-top chip layouts
Experience with floorplanning, power distribution, ESD, and multiple voltage domains
Familiarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high-speed interface circuits
Excellent communication and cross-functional leadership skills
SKILL or Perl scripting is a plus
Fluent in English
Skills
Cadence Virtuoso XL
PVS DRC/LVS/ERC
SKILL
Perl
Benefits
Annual incentive
Equity
Principal Analog Layout Engineer / Layout Lead
Job Description
NXP’s Smart Analog Interfaces is seeking a highly motivated Principal Analog Layout Engineer to join a dynamic team developing state-of-the-art analog and high-speed interface products. This role offers the opportunity to work on complex mixed-signal ICs for leading consumer and automotive applications while contributing to innovative custom silicon solutions.
The successful candidate will serve as both an analog layout lead for custom analog-on-top and digital-on-top projects and a hands-on analog block layout designer, collaborating closely with circuit designers, physical design engineers, and cross-functional teams to deliver high-quality products from concept through tapeout.
Key Responsibilities
•
Develop and lead block-level and top-level analog/mixed-signal layouts.
•
Drive floorplanning, power routing, ESD implementation, and chip integration.
•
Run and debug DRC, LVS, ERC, and extraction flows.
•
Collaborate with design, digital P&R, IO, ESD, package, test, and PDK teams.
•
Provide layout schedules, technical leadership, and customer communication.
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Identify layout risks and drive resolution of design and PDK issues.
•
Improve layout methodologies and automation.
Qualifications
•
BSEE or MSEE.
•
10+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.
•
Expert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC.
•
Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices.
•
Proven experience leading analog-on-top and digital-on-top chip layouts.
•
Experience with floorplanning, power distribution, ESD, and multiple voltage domains.
•
Familiarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high-speed interface circuits.
•
Excellent communication and cross-functional leadership skills.
•
Fluent in English
•
SKILL or Perl scripting is a plus.
Legal
NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
Benefits
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 61,000 € and 83,900 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
About the company
More information about NXP in Italy…