● Own package architecture from concept through production for Velaura SoCs.
● Partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability.
● Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches.
●Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.
● Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O.
●Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.
●Work with foundry, assembly, substrate, and test partners to successfully deliver products to production.
●Help define Velaura’s long-term packaging roadmap as future products evolve.