Find jobs
Pricing
Sign in
FIND JOBS
PRICING
SIGN IN
SIGN UP
← Back
CA
Cadence
Lead Design Engineer
Save
Tailor resume
Apply
Location
BANGALORE
Work mode
on-site
Type
full-time
Company size
10,000+ people
First seen
2w ago
Last seen
5d ago
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
About the role
Design verification of ASICs for Palladium.
Responsibilities
•
Position is based in Bangalore
•
Will have to work at IP, Sub-System and SOC level verification.
•
Test plan creation, functional coverage plan and coding of functional coverage bins.
•
Will be involved in post silicon validation/bring up.
Requirements
Job Requirements:
•
Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.
•
Experience in functional coverage/code coverage/assertions development and closure.
•
Experience in test plan creation.
•
Exposure to PCIe and LPDDR verification.
•
Strong debug skills
•
Should be process oriented and have a passion for scripting/automation.
•
Should be a good team player
•
Effective cross-team communication and documentation skill is strongly preferred.
Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields.
We’re doing work that matters. Help us solve what others can’t.
More roles at Cadence
Program Manager II
Security Receptionist
Intern Digital Implementation
Processor Core Logic Design/Architect
AI Engineer, Ontologies & Knowledge Graphs
Seekless
Product
Find jobs
Companies
Pricing
Legal
Privacy
Terms
Cookies
© 2026 SEEKLESS, INC. ALL RIGHTS RESERVED.
BUILT WITH CARE