Excellent Logic design, FSM design skills. Ability to model logic using HDL’s like System Verilog or VHDL using synthesizable design constructs.
Strong in HDL’s – System Verilog / VHDL, structured and layered coding practices including familiarity with OOPS concepts.
Must be willing to learn new technologies, get familiar with new standards.
Strong in digital design, Micro-Architecture, Design documentation and RTL coding for IP blocks.
Familiar with Armv7-A processor architecture like Cortex A7, Cortex A9 or any other processor.
Familiar with bus protocols like AXI, AHB and APB.
Masters Degree in Engineering with specialization in Electronics / VLSI from one of the reputed institutes with minimum of 5 years experience.