Sr. Tech Lead SRAM ROM Expert
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Before you apply
LocationBangalore
SeniorityLead
Experience10+ yrs
Company size10,000+ people
PostedNov 2, 2026 · 3d ago
Verified live2d ago
At a glanceSummarised by Seekless from the posting.
Define and drive next-generation SRAM and ROM architectures for embedded and standalone memory products
Own memory roadmap development, architectural trade-off analysis, and technology strategy across multiple product lines
Lead optimization of performance, power, area (PPA), yield, and reliability targets
Architect memory arrays, peripheral circuits, redundancy schemes, ECC, power-management features, and test methodologies
Collaborate with circuit design, layout, verification, product, and process technology teams from concept through silicon validation and production
Drive innovation in low-voltage operation, high-speed access, low-power techniques, and memory reliability
Develop architectural models for memory performance, power consumption, area, and yield prediction
Lead root-cause analysis of silicon issues and define architectural improvements for future generations
Mentor engineers and provide technical leadership across cross-functional teams
Influence long-term memory technology roadmaps and IP strategy
Bachelor's Degree (B.E./B.Tech.) in Electrical Engineering, Electronics Engineering, Electronics & Communication Engineering, or a closely related discipline
10+ years of experience in SRAM, ROM, embedded memory, custom memory, or memory compiler development
Deep expertise in memory architecture, bitcell and peripheral circuit design, redundancy, ECC, memory compilers, and advanced CMOS technologies
Strong understanding of memory characterization, silicon validation, reliability, and yield optimization
Proven track record of technical leadership, innovation, patent generation, and successful silicon delivery
Architect SRAM/ROM-based In-Memory Computing (IMC) solutions for AI/ML acceleration and edge-computing applications
Evaluate and develop digital, analog, and mixed-signal IMC architectures
Define compute-enabled memory macros supporting Vector-Matrix Multiplication (VMM) and Multiply-Accumulate (MAC) operations
Optimize energy efficiency, throughput, accuracy, and scalability for memory-centric AI workloads
Drive innovations involving ADC/DAC integration, quantization, calibration, and variation-tolerant compute architectures
Collaborate with AI accelerator, system architecture, and algorithm teams to enable next-generation intelligent computing solutions
Master's Degree (M.Tech./M.S.) in VLSI Design, Microelectronics, Semiconductor Technology, Integrated Circuit Design, or related specialization preferred
Ph.D. in VLSI, Memory Design, Computer Engineering, or related field is a plus
Experience in AI hardware, In-Memory Computing (IMC), or memory-centric computing architectures is highly desirable
Skills
SRAM
ROM
VMM
MAC
ADC/DAC
ECC
CMOS
Job Responsibilities:
•
Define and drive next-generation SRAM and ROM architectures for embedded and standalone memory products.
•
Own memory roadmap development, architectural trade-off analysis, and technology strategy across multiple product lines.
•
Lead optimization of performance, power, area (PPA), yield, and reliability targets.
•
Architect memory arrays, peripheral circuits, redundancy schemes, ECC, power-management features, and test methodologies.
•
Collaborate with circuit design, layout, verification, product, and process technology teams from concept through silicon validation and production.
•
Drive innovation in low-voltage operation, high-speed access, low-power techniques, and memory reliability.
•
Develop architectural models for memory performance, power consumption, area, and yield prediction.
•
Lead root-cause analysis of silicon issues and define architectural improvements for future generations.
•
Mentor engineers and provide technical leadership across cross-functional teams.
•
Influence long-term memory technology roadmaps and IP strategy.
Special Plus – In-Memory Computing (IMC)
Nice to have
•
Architect SRAM/ROM-based In-Memory Computing (IMC) solutions for AI/ML acceleration and edge-computing applications.
•
Evaluate and develop digital, analog, and mixed-signal IMC architectures.
•
Define compute-enabled memory macros supporting Vector-Matrix Multiplication (VMM) and Multiply-Accumulate (MAC) operations.
•
Optimize energy efficiency, throughput, accuracy, and scalability for memory-centric AI workloads.
•
Drive innovations involving ADC/DAC integration, quantization, calibration, and variation-tolerant compute architectures.
•
Collaborate with AI accelerator, system architecture, and algorithm teams to enable next-generation intelligent computing solutions.
Education
•
Bachelor’s Degree (B.E./B.Tech.) in Electrical Engineering, Electronics Engineering, Electronics & Communication Engineering, or a closely related discipline.
•
Master’s Degree (M.Tech./M.S.) in VLSI Design, Microelectronics, Semiconductor Technology, Integrated Circuit Design, or related specialization preferred.
•
Ph.D. in VLSI, Memory Design, Computer Engineering, or related field is a plus.
Experience & Skills
•
10+ years of experience in SRAM, ROM, embedded memory, custom memory, or memory compiler development.
•
Deep expertise in memory architecture, bitcell and peripheral circuit design, redundancy, ECC, memory compilers, and advanced CMOS technologies.
•
Strong understanding of memory characterization, silicon validation, reliability, and yield optimization.
•
Proven track record of technical leadership, innovation, patent generation, and successful silicon delivery.
•
Experience in AI hardware, In-Memory Computing (IMC), or memory-centric computing architectures is highly desirable.
About the company
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