Design Verification Engineer
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Before you apply
SalaryNo pay range posted
LocationUSA-CA San Jose Innovation Drive
Typefull-time
SenioritySenior
Experience12+ yrs
DepartmentEngineering
EquityIncluded
Company size10,000+ people
PostedOct 22, 2026 · 2w ago
Verified live4d ago
At a glanceSummarised by Seekless from the posting.
Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
12+ year's relevant industry work experience
Experience in verifying designs at system level and block level
Fluent knowledge of RTL verification methodologies including System Verilog
Strong experience in ASIC design verification flows and DV methodologies
Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills
Strong and independent design debugging capability
Strong verbal and written communication skills
Demonstrated ability to analyze and resolve complex verification trade-off scenarios
Highly productive individual contributor with demonstrated technical capability in system and sub-block level verification
Experience with hardware design and debug, C++/SystemC and other programming languages
Experience working with Emulators and FPGA based prototyping
Familiarity with overall chip design methodologies and tools
Must have legal authorization to work in the US
We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law
We will also consider qualified applicants with arrest and conviction records consistent with local law
Skills
System Verilog
UVM
RTL
OVM
C
C++
Perl
SystemC
Emulators
FPGA
Benefits
Health insurance
Dental insurance
Vision insurance
401(k)
Employee stock purchase plan
Employee assistance program
Paid holidays
Paid sick leave
Vacation time
Paid family leave
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Job Description:
The ASIC Product Division at Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements.
Responsibilities include:
•
Verification environment development using modern verification techniques (System Verilog and UVM)
•
Designing verification components such as UVM agents, and behavioral models
•
Implementing coverage and assertions using System Verilog
•
Developing random and directed test cases against the specification
•
Analyzing and debugging simulation failures, as well as analyzing coverage results
Job Requirements:
•
A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
•
12+ year’s relevant industry work experience.
•
Experience in verifying designs at system level and block level.
•
Fluent knowledge of RTL verification methodologies including System Verilog.
•
Strong experience in ASIC design verification flows and DV methodologies
•
Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
•
Strong and independent design debugging capability.
•
Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members.
•
Demonstrated ability to analyze and resolve complex verification trade-off scenarios.
•
Highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification
•
Must have legal authorization to work in the US
The candidate should have expertise in some (or preferably all) of the following areas:
•
Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus.
•
Experience working with Emulators and FPGA based prototyping is a plus.
•
Familiarity with overall chip design methodologies and tools
•
Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred
Compensation and Benefits
The annual base salary range for this position is USD To USD
As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.