Responsibilities include:
· Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems
· Develop constraints, run synthesis, perform low power, timing and equivalence checks and closure
· Work closely with RTL designer, physical design, low power teams to optimize performance, area and power
· Generate, review and validate design constraints to achieve timing closure of high speed design
· Develop floor-planning and CTS guidelines for layout
· Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure
· Perform in-house quality check before P&R and after P&R
· Constraint management tool and Verilog coding experience
· Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
· Improve existing process and enhance team work efficiency