● Deep expertise in memory subsystem design: caches, coherency, memory controllers (e.g., LPDDR/DDR/HBM), on-chip SRAM organization, address translation, and memory protection.
● Hands-on experience designing or significantly extending DMA engines, data-movement accelerators, or similar high-bandwidth data-path logic —including descriptor-based DMA, multi-channel arbitration, QoS, and outstanding-transaction management.
● Working knowledge of standard interconnect and coherency protocols (e.g., AXI, CHI, ACE) and their performance implications.
● Experience with SMMU/IOMMU design or integration, virtualization, and DMA isolation for safety or security.
● Familiarity with RAS features in memory and data paths, such as ECC, poisoning, and error reporting.
● Experience with NoC fabrics, virtual channels, and QoS mechanisms for memory traffic.
● Knowledge of functional safety (e.g., ISO 26262/ASIL) as it applies to memoryand data-path design.
● Experience with AI, machine learning, or edge AI hardware, especially tensordata-movement patterns and tiling strategies.
● Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
● Knowledge of low-power design techniques and power management architectures.
● Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
● Experience using modern AI tools and workflows to accelerate engineering productivity.
● Background in CPUs and memory subsystems, GPUs, AI accelerators,networking and communications silicon, storage and data movementarchitectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS), aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.