Or BS in EE with 8+ years of experience in Digital Implementation, either as a design engineer or as a product engineer
Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including RTL synthesis, placement optimization, clock tree synthesis, routing optimization and silicon signoff.
Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.
Exposure to, and solid understanding of, hierarchical design methodologies and low power design
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting