DFT Engineer
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Before you apply
Salary$133k – $185k
LocationBengaluru, Karnataka, India
Typefull-time
SeniorityLead
Experience5+ yrs
DepartmentDesign for Test CCE1
Company size501–1,000 people
PostedSep 21, 2026 · 1mo ago
Verified live3d ago
At a glanceSummarised by Seekless from the posting.
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of digital design experience, including at least one full chip from spec to tapeout
Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
Hands-on experience with timing closure, CDC, lint, and low-power design techniques
Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
MS or PhD in Electrical Engineering or Computer Engineering
Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
Familiarity with formal verification, emulation, or assertion-based methodologies
Background in advanced process nodes (7nm, 5nm, or below)
Strong debug skills across pre-silicon and post-silicon environments
Skills
Verilog
SystemVerilog
PCIe
Ethernet
CXL
UALink
UCIe
COSMOS
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the role
Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world’s largest AI clusters. You’ll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.
This is a high-impact technical role at a hyper-growth company. You’ll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.
Key Responsibilities
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RTL Design & Implementation
•
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
•
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
•
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
•
Cross-Functional Execution
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Partner with architecture to translate specifications into implementation-ready microarchitecture
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Collaborate with verification on testplans, coverage closure, and bug triage
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Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
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Technical Leadership & Quality
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Mentor junior engineers and contribute to design methodology, scripts, and best practices
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Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
•
Drive structured, data-driven design decisions in support of aggressive tapeout schedules
Basic Qualifications
•
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
•
5+ years of digital design experience, including at least one full chip from spec to tapeout
•
Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
•
Hands-on experience with timing closure, CDC, lint, and low-power design techniques
•
Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Preferred Qualifications
•
MS or PhD in Electrical Engineering or Computer Engineering
•
Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
•
Familiarity with formal verification, emulation, or assertion-based methodologies
•
Background in advanced process nodes (7nm, 5nm, or below)
•
Strong debug skills across pre-silicon and post-silicon environments
Benefits
Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Legal
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.