Design Verification Engineer - Interface IP
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Before you apply
SalaryNo pay range posted
LocationSan Jose
Work modeon-site
Typefull-time
SenioritySenior
Experience5+ yrs
DepartmentASIC
Company size501–1,000 people
PostedSep 11, 2025 · 1y ago
Verified live7h ago
May no longer be actively hiring
Posted by the company on Sep 11, 202556% of this company's open roles have been listed for 90+ daysNo pay range listed, though California requires one
At a glanceSummarised by Seekless from the posting.
5+ years of design verification experience
Deep technical ability and creativity to tackle complex verification challenges
Hands-on experience with SystemVerilog/UVM
Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
Thrives in a fast-paced startup environment and can take ownership with minimal direction
Collaborates naturally with cross-functional teams and communicates technical insights clearly
Experience handling vendors and integration of IP/VIPs
Skills
UVM
SystemVerilog
PCIe
Ethernet
AXI
AMBA
ARM
ARC
Benefits
Health insurance
Dental insurance
Vision insurance
Housing subsidy
Relocation support
Wellness benefits
Meal benefits
Unlimited compute budget
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.
Key responsibilities
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End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
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Understand vendor IP configurations and handle handshake with internal IP team
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Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
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Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
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Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.
You may be a good fit if you have
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5+ years of design verification experience
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You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
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You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
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You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
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You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
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You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.
Strong candidates may also have experience with
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Experience handling vendors and integration of IP/VIP’s
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UVM/System Verilog
Benefits
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Medical, dental, and vision packages with generous premium coverage
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$500 per month credit for waiving medical benefits
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Housing subsidy of $2.5k per month for those living within walking distance of the office
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Relocation support for those moving to San Jose (Santana Row)
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Various wellness benefits covering fitness, mental health, and more
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Daily lunch + dinner in our office
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Unlimited compute budget subject to ROI justification
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.