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Samsung Electronics

SRAM Memory Design

LocationSSIR, Angkor West, Bangalore, India
Typefull-time
SenioritySenior
Experience4–10 yrs
Company size10,000+ people
First seenOct 6, 2026 · 5d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Must have11
Master/Bachelor in electronics
Understanding of RC network and FINFET fundamentals
Custom or Compiler SRAM/ROM development experience
Fundamentals of process variability and its effect on memory design
Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
Strong understanding of circuit design fundamentals
Critical path modelling concept, various type of models (RC, C, Pai, ladder)
Good knowledge of semiconductor physics
Analysing layout and understanding of LLE effects
Experience – 4 to 10 Years of experience
B.Tech/B.E/M.Tech/M.E
Nice to have1
Working experience in preferably Memory design
Skills
SRAM
ROM
FINFET
Position Summary
Position: SRAM Memory Design Engineer:
Responsibilities
Roles and Responsibilities:
• Design highly competitive circuits to meet performance/power specifications requested by customers
• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
• Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.
• Own the responsibility from SPEC to GDS and DK delivery.
• Review circuits, robustness reports and identify potential robustness issues.
• Review Layouts and suggest improvement areas to achieve competitive PPA
• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
• Must be able to communicate effectively across different teams.
Role and Responsibilities
Requirements
Skills & Experience:
• Master/Bachelor in electronics
• Working experience in preferably Memory design
• Understanding of RC network and FINFET fundamentals are necessary.
• Custom or Compiler SRAM/ROM development experience
• Fundamentals of process variability and its effect on memory design
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
• Strong understanding of circuit design fundamentals
• Critical path modelling concept, various type of models ( RC, C, Pai,ladder)
• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc
• Analysing layout and understanding of LLE effects.
Skills and Qualifications
Experience – 4 to 10 Years of experience
Qualifications: B.Tech/B.E/M.Tech/M.E
Legal
Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law
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