• Design and implement RTL using SystemVerilog with consideration for timing, power, and area
• Perform FPGA prototyping, validation, and hardware bring-up for digital designs
• Develop and execute simulation and debugging strategies at block and subsystem levels
• Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals
• Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns
• Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance
• Participate in design reviews and contribute to improving design quality and best practices