Principal Physical Verification Engineer
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Before you apply
Salary$144k – $230k
LocationUSA-CA San Jose Innovation Drive
Work modeon-site
Typefull-time
SeniorityLead
Experience12+ yrs
DepartmentASIC Products Division (APD) - Physical Design Team
EquityIncluded
Company size10,000+ people
PostedOct 23, 2026 · 2w ago
Verified live3d ago
At a glanceSummarised by Seekless from the posting.
12+ years of relevant experience
Bachelor's degree in Electrical Engineering or Electronics Engineering
Hands-on experience in running physical verification (LVS, DRC, ERC, PERC)
Experience with EDA tools and flows such as ICV, Calibre and Pegasus
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
Electrical Rule Checking (ERC/PERC): Analyze ESD, latch-up, floating gates, and power-domain isolation vulnerabilities
Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules
Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules
Collaborate with physical design (P&R) to resolve critical top-level integration bottlenecks
Experience in scripting languages like Python, Tcl, or Perl
Excellent verbal and written communication skills
Must work in person at our San Jose site and no remote work allowed
Skills
ICV
Calibre
Pegasus
Python
Tcl
Perl
DRC
LVS
ERC
PERC
Benefits
Medical insurance
Dental insurance
Vision insurance
401(k)
Company matching
Employee stock purchase plan
Employee assistance program
Paid holidays
Paid sick leave
Vacation time
Paid family leave
Other leaves of absence
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Job Description:
Principal Physical Design Engineer — ASIC Products Division (APD)
Location: San Jose, CA
Position Type: Full-Time
Who We Are — Physical Design Team in APD
Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.
The Physical Design team within APD is the world-class execution engine behind the industry’s most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.
Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundry rules, DFM and experience in silicon tape-out and RTO tapeout.
Responsibilities:
•
Execution of Chip level Physical Verification & Issue resolution
•
Work on setting up DRM runsets for advance nodes and tool flows
•
Manage and guide rules related to Top level Floorplan, I/O and bump planning
•
Resolve physical design issues related to chip integration and assembly
•
Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
•
Develop best practice guidelines for physical verification flows and runtime optimizations
Preferred qualifications:
•
Hands-on experience in running physical verification (LVS,DRC,ERC,PERC)
•
Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
•
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
•
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
•
Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities.
•
Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules.
•
Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
•
Collaborate with physical design (P&R) to resolve critical top-level integration bottlenecks.
•
Experience in scripting languages like Python, Tcl, or Perl
•
Excellent verbal and written communication skills
•
Must work in person at our San Jose site and no remote work allowed
Education and Experience Requirements:
•
Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering
12+ Years of relevant experience
Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.