● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, or a related discipline.
● Strong understanding of computer architecture, high-performance design concepts, and micro-architecture tradeoffs.
● Experience working on AI accelerators, high-performance compute, networking,CPU, GPU, or memory subsystem designs.
● Experience with low-power implementation flows, UPF-based design methodologies, power domains, level shifters, isolation cells, retention strategies, and power-aware sign-off.
● Good understanding of DFT requirements and their impact on physical implementation, timing, routing, and sign-off.
● Experience developing or improving physical design methodologies, implementation recipes, and CAD automation flows.
● Track record of leading complex block-level or subsystem-level physical design execution through tapeout.
● Ability to mentor junior engineers and provide technical guidance across implementation and sign-off activities.
● Experience with sub-5nm or leading-edge technology nodes.
● Experience with high-performance AI, CPU, GPU, VPU, DDR, NoC, or memory controller designs.
● Experience with hierarchical design implementation and top-level integration.
● Knowledge of advanced clocking techniques, useful skew, clock mesh, or complex CTS methodologies.
● Familiarity with package-aware implementation, bump planning, power grid design, and chip-level integration.
● Experience with timing ECO, functional ECO, metal ECO, and late-stage designclosure.
● Exposure to silicon bring-up, correlation, production support, and post-silicon debug.
● Experience driving physical design methodology improvements and EDA automation.
● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.
● Passion for solving hard design closure problems and delivering high-quality silicon under aggressive product schedules.
● Background in RTL-to-GDSII physical implementation; high-performance block-level and subsystem-level physical design; synthesis, floorplanning, placement, CTS, routing, and timing closure; Static Timing Analysis and
multi-corner multi-mode design closure; advanced-node physical design implementation; physical verification including DRC, LVS, ERC, antenna, density,and metal fill; power integrity, EM/IR analysis, and sign-off; low-power
implementation and power-aware design closure; physical design methodology, flow development, and automation; or cross-functional silicon development in advanced semiconductor environments.