Necessary Skills / Attributes
.• Project Management. Working experience in complex IP Design to meet market leading PPA metrics
• Experience in designing and RTL coding using Verilog /System Verilog/VHDL.
• Design QC using lint/CDC/DFT
• Compile , elaboration and simulations for QC. Experience with VCS/NCsim, Verdi, and Spyglass.
• Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management.
• Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures.
• Experience in writing functional design doc and/or functional specifications.
• Experience in synthesis using Synopsys Design Compiler ( DC) and developing timing constraints ( SDC) and Timing analysis.
• Experience in developing/understanding of ECOs
• Working experience in teams with collaboration of effort between Verification, SoC integration, Physical Design and DFT Additional Qualifications (preferred)