SiFive

Websitesifive.com

Company size501–1,000 people

Annual pay$182k – $250k

Pay rows show the middle half of posted pay: annual from 26 roles.

128 Open RolesLast checked 1d ago

Engineering — 24 roles

Interconnect Design Engineer

Santa Clara, California, United States +3 morefull-timeVerified 1d ago

LeadChiselScalaVerilogSystem Verilog

Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

Hyderabad, Indiafull-timeVerified 1d ago

Lead1+ yrsSystem VerilogUVMPythonPerl

Senior Staff Design Verification Engineer – Coherent Interconnect

Boston, Massachusetts, United States +1 morefull-timeVerified 1d ago

Lead8+ yrsSystemVerilogPythonCHIACE

Staff Engineer, Physical Design

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead8+ yrsSynopsys Fusion CompilerPrimeTimeCadence InnovusTempus

Senior Staff Software Quality Assurance Engineer

Hsinchu, Taiwanon-sitefull-timeVerified 1d ago

Lead8+ yrsPyTestRobot FrameworkGitJenkins

Staff Design Verification Engineer – Cache Verification

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead7+ yrsSystemVerilogUVMPythonC/C++

Staff Design Verification Engineer – Cache Verification

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead7+ yrsSystemVerilogUVMPythonC

Staff Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogUVMPythonC

Platform Technologies Language & Frontend Design Engineer

Santa Clara, California, United States +2 morefull-time$140k – $171kVerified 1d ago

ScalaPythonMLIRC++

Principal Design Verification Engineer – CPU Core Frontend

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead12+ yrsPythonRISC-V

Senior Staff Design Verification Engineer – Coherent Interconnect

Boston, Massachusetts, United States +1 morefull-timeVerified 1d ago

Lead8+ yrsSystemVerilogPythonCHIACE

Power Management Design Engineer

Santa Clara, California, United States +2 morefull-time$140k – $171kVerified 1d ago

Mid3+ yrsVerilogSystemVerilogVDHLSpyglass

Senior CPU Design Verification Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Senior5–10 yrsSystemVerilogUVMVCSXcelium

Staff Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogUVMPythonC

Sr. Staff Engineer - Design Verification

Hyderabad, Indiafull-timeVerified 1d ago

Lead10+ yrsSystemVerilogUVMSVAVerdi

Staff Design Verification Engineer – CPU Core Formal Verification

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7+ yrsPythonPerlTclRTL

Staff Design Verification Engineer – CPU Core Verification (Vector)

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogPythonCC++

Senior Design Verification Engineer – CPU Core Verification (Vector)

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Senior5+ yrsSystemVerilogRISC-V Vector Extension (RVV)RISC-V

Senior Design Verification Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Senior5–10 yrsSystemVerilogUVMSVAVCS

Staff Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogUVMPythonC/C++

Senior Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Senior3+ yrsSystemVerilogUVMPython

Senior Engineer - Design Verification

Ahmedabad, Indiafull-timeVerified 1d ago

Senior5+ yrsSystemVerilogUVMAXICHI

Principal Design Verification Engineer – CPU Subsystem Power Management

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead12+ yrsSystemVerilogPython

Power Management Design Engineer

Cambridge, England, United Kingdom +2 morefull-timeVerified 1d ago

Mid3+ yrsVerilogSystemVerilogVDHLSpyglass

AI/ML Software Team — 1 role

AI/ML Software Engineer

Hsinchu, TaiwanVerified 1d ago

C++PythonMLIRIREE

CPU Design Verification — 1 role

Staff Design Verification Engineer – CPU Core Formal Verification

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7+ yrsPythonPerlTcl

Design Verification — 1 role

Staff Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogUVMPythonC

Design Verification Infrastructure — 1 role

Intern - Design Verification Infrastructure Engineer - Platform

Santa Clara, California, United States +3 morefull-timeVerified 1d ago

EntryChiselCIRCTMLIRScala

Program Management Office (PMO) — 1 role

Technical Program Manager

Bengaluru, Indiafull-timeVerified 1d ago

GitGitHubJIRAConfluence

Sales — 1 role

Director of Sales, Commercial Accounts

Santa Clara, California, United Statesfull-timeVerified 1d ago

Director5+ yrsCRM

Software Architecture — 1 role

Datacenter System Software Architect

Santa Clara, CA +49 morefull-time$231k – $283kVerified 1d ago

LeadLinuxRISC-VCPCIe

Other — 97 roles

Sr Engineer - Physical Design

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior4+ yrsSynopsys Fusion CompilerSynopsys PrimeTimeCadence InnovusCadence Tempus

Staff Engineer, Physical Design - High Speed Interconnects

Bengaluru, Karnataka, IndiaVerified 1d ago

Lead7+ yrsSynopsysCadence

Staff Software Application Engineer

Santa Clara, California, United Statesfull-time$159k – $194kVerified 1d ago

Lead5+ yrsCC++assemblyGNU tools

Principal Field Application Engineer

Shanghai, Chinafull-timeVerified 1d ago

Lead5+ yrsRTLFPGACassembly

Strategic Sales Director

Santa Clara, California, United StatesVerified 1d ago

Director10+ yrsCRM

Staff Engineer - DV

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7–12 yrsSystem VerilogUVMPythonAXI

Staff Engineer - Design Verification

Hyderabad, Indiafull-timeVerified 1d ago

Lead7+ yrsSystemVerilogUVM

Performance Architect

Hsinchu, TaiwanVerified 1d ago

AssemblyC/C++Waveform analysisGit

Core Performance Architect

Santa Clara, California, United States +3 morefull-time$254k – $311kVerified 1d ago

Lead10+ yrsRTLFPGA

Intern - Design Verification Infrastructure Engineer - Platform

Santa Clara, California, United States +3 morefull-timeVerified 1d ago

EntryChiselCIRCTMLIRScala

SOC Architect

Santa Clara, California, United States +4 morefull-time$254k – $311kVerified 1d ago

Lead10+ yrs

Design Verification Infrastructure Engineer - Software and Build

Bengaluru, Karnataka, IndiaVerified 1d ago

Senior5+ yrsWakeEDA tools

Staff Design Verification Engineer – Coherent Interconnect

Boston, Massachusetts, United States +1 morefull-timeVerified 1d ago

Lead7+ yrsCXLCHIACEAXI

Senior Staff Engineer, Physical Design - NoC

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead10+ yrsRTLSynopsysCadenceGDS

Software Engineer - Platform Technologies

Austin, Texas, United States +3 moreVerified 1d ago

C++Pythonmakecmake

Staff Engineer, Physical Design - Cores

Bengaluru, Karnataka, IndiaVerified 1d ago

Lead7+ yrsSynopsysCadence

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsSystem VerilogUVMChiselScala

Principal Design Verification Engineer – High Performance CPU Subsystem

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead12+ yrsPythonRTLformal verificationemulation

Debug/Trace/Profiling Design Engineer

La Ciotat, France +3 morefull-timeVerified 1d ago

Senior7+ yrsJTAGcJTAGVerilogSystem Verilog

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

LeadSystem VerilogUVMChiselScala

Staff RTL Design Engineer - CPU Midcore

Cambridge, England, United Kingdomfull-timeVerified 1d ago

Lead5+ yrsChiselVerilogSystem VerilogVHDL

Design Verification Infrastructure Engineer - Software

Hsinchu, Taiwanfull-timeVerified 1d ago

ScalaChiselPythonDevOps

Staff RTL Design Engineer - CPU LS/PF/MMU

Santa Clara, California, United States +1 morefull-time$179k – $219kVerified 1d ago

Lead3+ yrsChiselFIRRTLVerilogSystem Verilog

Staff Design Verification Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead5+ yrs

Senior IP Verification Engineer(IOMMU-N)

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior3+ yrsSystem VerilogVerilogPythonPerl

Workload / Performance Model Lead

Santa Clara, California, United States +3 morefull-time$231k – $283kVerified 1d ago

Lead10+ yrsRISC-Vgit

Senior Staff Verification Engineer For Worldguard

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead10+ yrsSystemVerilogUVMPythonPerl

Principal Interconnect Design Engineer

Santa Clara, CA +3 morefull-time$231k – $283kVerified 1d ago

LeadChiselScalaVerilogSystem Verilog

CPU Design Verification Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Lead5+ yrsSystem VerilogUVM

Senior Design Verification Infrastructure Engineer - VIPs and Testbench

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior3+ yrsSystem VerilogUVMScalaChisel

Staff Engineer, Physical Design

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead8+ yrsSynopsys Fusion CompilerSynopsys PrimeTimeCadence InnovusCadence Tempus

Staff Engineer - CPU Verification

Hyderabad, Indiafull-timeVerified 1d ago

Lead7+ yrsUVMSystemVerilogRISC-VARM

Principal Design Verification Engineer – CPU Core LSU

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead12+ yrsPythonRTL

CPU Power-Management Design Engineer

Santa Clara, California, United States +3 morefull-time$179k – $219kVerified 1d ago

Mid3+ yrsVerilogSystemVerilogVDHLSpyglass

Linux Kernel Architect

Santa Clara, California, United States +11 morefull-timeVerified 1d ago

LeadLinuxOpenSBIRISC-VDevicetree

Confidential Computing Software Architect

Santa Clara, California, United States +12 moreVerified 1d ago

SeniorCLinuxRustAda SPARK

Staff / Sr. Staff Engineer DV

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsUVMVCSUPFPython

Principal Design Verification Engineer – CPU Core Hardware Prefetch

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead12+ yrsPython

Staff System Validation Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead5+ yrsFPGAScalaChiselLinux

Senior Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Senior3+ yrsSystemVerilogUVM

Senior Design Verification Engineer – High Performance CPU Core

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Senior3+ yrsSystemVerilogUVM

Power Infrastructure Engineer

Santa Clara, California, United States +3 morefull-time$206k – $251kVerified 1d ago

Senior8+ yrsRTLFPGAASIC

Power Infrastructure Lead

Santa Clara, California, United States +4 morefull-time$206k – $251kVerified 1d ago

Lead5+ yrsPythonRTLFPGAASIC

Core Performance Architect

Santa Clara, California, United States +3 morefull-time$179k – $219kVerified 1d ago

Lead3+ yrsRTLFPGAIntegrated Logic Analyzer

Full-Stack Staff Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Lead10+ yrsPythonDjangoPostgreSQLRedis

Principal Design Verification Engineer – CPU Coherent Interconnect

Santa Clara, California, United States +2 morefull-time$231k – $283kVerified 1d ago

Lead12+ yrsSystemVerilogPython

Zebu flow Engineer

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Entry1+ yrsPythonBASHVerilogFPGA

Senior Staff RTL Design Engineer - CPU Frontend

Santa Clara, California, United States +2 morefull-time$206k – $251kVerified 1d ago

Lead7+ yrsChiselFIRRTLVerilogSystem Verilog

Senior / Staff Design Verification Engineer

Ahmedabad, Indiafull-timeVerified 1d ago

Lead5+ yrsSystemVerilogUVMPythonPerl

Software Engineer - FPGA-Accelerated RTL Simulation

Berkeley, California, United Statesfull-time$179k – $219kVerified 1d ago

Senior7+ yrsC++C++20FireSimChisel

Power Model Engineer

Santa Clara, California, United States +1 morefull-time$179k – $219kVerified 1d ago

Senior3+ yrsRTLverification/validationbackend flowsFPGA flows

Product Power Engineer

Santa Clara, California, United States +3 morefull-time$179k – $219kVerified 1d ago

Senior3+ yrsRTLASICFPGAHW development

Design Verification Engineer to Staff Engineer (Unit Level Test)

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead3+ yrsSystemVerilogUVMVerdiDVE

Power Management Design Engineer

Santa Clara, California, United States +3 morefull-time$159k – $194kVerified 1d ago

Mid3+ yrsVerilogSystemVerilogVDHLSpyglass

Design Verification Infrastructure Engineer - Platform

Santa Clara, California, United States +3 morefull-time$159k – $194kVerified 1d ago

SeniorPythonChiselCIRCTMLIR

Senior RTL Design Engineer - CPU Frontend

Santa Clara, California, United States +2 morefull-time$159k – $194kVerified 1d ago

Senior3+ yrsChiselVerilogSystem VerilogVHDL

Product Power Engineer

Santa Clara, California, United States +3 morefull-time$206k – $251kVerified 1d ago

Senior5+ yrsRTLFPGAASIC

Core Performance Architect

Santa Clara, California, United States +3 morefull-time$179k – $219kVerified 1d ago

Senior3+ yrsRTLFPGAIntegrated Logic Analyzer

Interconnect Design Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

SeniorChiselScalaVerilogSystem Verilog

Core Performance Architect

Santa Clara, California, United States +3 morefull-time$159k – $194kVerified 1d ago

Lead1+ yrsRTLFPGAIntegrated Logic Analyzer

Sr Engineer, Low Power Verification & Formal Equivalence

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior3+ yrsUPFSynopsys VC Low PowerVCLPSynopsys Formality

Staff Design Verification Engineer – CPU Core Verification (ALU)

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogPythonCC++

Staff Design Verification Engineer – Coherent Interconnect (CHI)

Boston, Massachusetts, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsSystemVerilogPythonARM CHIRISC-V

Staff Engineer - Physical Design

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsSynopsys Fusion CompilerSynopsys PrimeTimeCadence InnovusCadence Tempus

Staff Design Verification

Hyderabad, Indiafull-timeVerified 1d ago

Lead8+ yrsSystemVerilogUVMSVAVCS

Senior Engineer - CPU DV

Hyderabad, Indiafull-timeVerified 1d ago

SeniorSystem VerilogUVMARM ISARISC-V

Staff Design Verification Engineer – CPU Core Formal Verification

Austin, Texas, United States +1 morefull-timeVerified 1d ago

Lead7–8 yrsPythonPerlTcl

Sr. Staff AI System Software Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead8+ yrsCC++LinuxBSD

Engineer II, Physical Design

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior2+ yrsSynopsys Fusion CompilerICC2PrimeTimeStarRC

Staff - Formal Verification Engineer

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead8+ yrsChiselVC FormalJasperGoldVHDL

Engineer II, Physical Design - Cores

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Entry3+ yrsPythonTclBashPerl

Staff Formal Verification Engineer

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsChiselVC FormalJasperGoldVHDL

Senior Engineer, Physical Design - Interconnects

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior4+ yrsRISC-VNoCSynopsysCadence

Product Power Engineer

Santa Clara, California, United States +3 morefull-time$179k – $219kVerified 1d ago

Senior5+ yrsRTLFPGAASIC

Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead15+ yrsSynopsys Fusion Design PlatformFusion CompilerIC Compiler IIPrimeTime

Staff Design Verification Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Lead8+ yrsSystem VerilogUVMSVA

Sr Engineer, CPU Implementation & Flow Automation

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior3+ yrsSynopsys Fusion CompilerICC2PrimeTimeStarRC

Senior Customer Release Engineer

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior4+ yrsPythonJSONYAMLIP-XACT

Senior Software Engineer, AI/ML Heterogeneous Systems

Hsinchu, Taiwanfull-timeVerified 1d ago

Senior3+ yrsC++PythonCUDAROCm

Sr Staff Static Timing Analysis (STA) Lead

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead10+ yrsSynopsys PrimeTimeSynopsys FusionCompilerMachine Learning

Senior Full Stack Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Senior5+ yrsPythonJavaScriptTypeScriptVS Code

Staff System Software Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead5+ yrsCLinuxBSDPCIe

Staff Physical Design Engineer: CPU Implementation & Flow Automation

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsSynopsys Fusion CompilerICC2PrimeTimeStarRC

Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior4+ yrsSystemVerilogUVMPythonC/C++

Staff RTL Design Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead5+ yrsVerilogSystem VerilogVHDLRISC-V

Distinguished Formal Verification Architect

Santa Clara, California, United States +2 morefull-time$280k – $342kVerified 1d ago

LeadVCFormalJasper GoldScalaOCaml

Performance benchmarking and Infrastructure Engineer to Senior Engineer

Hsinchu, TaiwanVerified 1d ago

SeniorC/C++Python

Senior CPU Formal Verification Engineer

Hyderabad, India +1 morefull-timeVerified 1d ago

Senior5+ yrsChiselVC FormalJasperGoldVHDL

Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Senior4+ yrsSystemVerilogPythonCC++

System Validation Engineer to Staff Engineer

Hsinchu, Taiwanfull-timeVerified 1d ago

Lead3+ yrsScalaChisel

Lead Debug/Trace/Profiling Design Engineer

La Ciotat, France +3 morefull-timeVerified 1d ago

Lead7+ yrsChiselScalaVerilogSystem Verilog

Principal Field Application Engineer

Shanghai, Chinafull-timeVerified 1d ago

Lead5+ yrsCPU architectureSoC architectureRTLimplementation flows

Java VM Software Performance Analysis Engineer

Hsinchu, TaiwanVerified 1d ago

SeniorperfftraceeBPFasync-profiler

Senior Design Verification Engineer

Hsinchu, TaiwanVerified 1d ago

Senior3+ yrsCC++PythonSystemVerilog

System Validation Engineer (New Grads)

Hsinchu, Taiwan +1 moreVerified 1d ago

EntryPythonBASHVerilogLinux

Senior CPU Design Verification Engineer

Hyderabad, Indiafull-timeVerified 1d ago

Senior5–10 yrsSystemVerilogUVMSVAVCS

Staff Engineer Formal(IOMMU-N)

Bengaluru, Karnataka, Indiafull-timeVerified 1d ago

Lead7+ yrsScalaChiselTCLRISC-V

Jobs by role

Software Engineer jobs26,000+

Full Stack Engineer jobs2,700+

QA and Test Engineer jobs3,500+

Program Manager jobs4,600+

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