At a glanceSummarised by Seekless from the posting.
Must have11
BS/MS/PhD in EE, CE, CS, or related field
8+ years of hands-on ASIC/SoC/IP design verification experience
Significant experience verifying out-of-order or superscalar CPU cores or similarly complex execution pipelines
Strong proficiency in SystemVerilog and UVM
Deep understanding of CPU micro-architecture including front-end, rename, schedulers, ROB, LSU, L1 caches, TLBs, MMU, and coherence interfaces
Solid experience with constrained-random, coverage-driven verification
Writing and debugging SVA assertions
Experience with major simulators (VCS, Xcelium, Questa) and debug tools (Verdi/DVE)
Strong problem-solving and debug skills for complex concurrency/ordering issues
Proven ability to drive technical topics across teams and to completion
Clear communication, both written and verbal
Eligibility3
Successful background and reference checks
Satisfactory proof of right to work in India
Any offer contingent on Company verifying authorized access to export-controlled technology or obtaining necessary export license(s)
Skills
SystemVerilog
UVM
SVA
VCS
Xcelium
Questa
Verdi
DVE
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Role Summary
We are looking for a Staff Design Verification Engineer to lead the verification of complex out‑of‑order (OOO) CPU cores and memory subsystems. In this role you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.
LSU, store buffer, speculative loads/stores, atomics and fences.
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L1 caches, TLBs, MMU, and coherence interfaces.
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Solid experience with:
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Constrained‑random, coverage‑driven verification.
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Writing and debugging SVA assertions.
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Major simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
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Soft Skills:
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Strong problem‑solving and debug skills for complex concurrency/ordering issues.
•
Proven ability to drive technical topics across teams and to completion.
•
Clear communication, both written and verbal; able to present designs, plans, and status to technical and non‑technical stakeholders.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.