At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
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The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
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The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
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The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
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The candidate will work closely with RTL design team to ensure successful tapeouts.
Requirements
Requirement:
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BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
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Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
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Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
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Able to assume responsibility for a variety of technical tasks and to work independently
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Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
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Self-motivated, able to work as a team player, and good English communication skills
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