Lead Design Verification Engineer
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Before you apply
LocationPenang 15, Penang, Malaysia
Work modeon-site
Typefull-time
SeniorityLead
Experience10+ yrs
Company size1,001–5,000 people
PostedOct 27, 2026 · 1w ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience
10+ years of technical experience
Pre Silicon Validation/Verification experience
OVM/UVM, System Verilog, constrained random verification methodologies
Design Verification with developing, maintaining, and executing complex IPs and/or SOCs
Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies
Experience in PCIe or UCIe PHY Verification
Skills
OVM
UVM
System Verilog
PCIe
UCIe
Job Details:
Job Description:
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Performs functional logic verification of an FPGA to ensure design will meet specification requirements.
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Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
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Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.
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Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
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Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
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May also collaborate with systems and software engineers to support integration testing of the FPGA.
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Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
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Maintains and improves existing functional verification infrastructure and methodology.
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Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Qualifications:
Minimal Qualification:
• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience.
• Related technical experience should be in/with: Pre Silicon Validation/Verification.
• OVM/UVM, System Verilog, constrained random verification methodologies.
Nice to have
Preferred Qualification:
• Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
• Experience in PCIe or UCIe PHY Verification.
Job Type:
Regular
Shift:
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.