ASIC Design Engineer, PCIe IP Enablement
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Before you apply
LocationCA,ON,Markham-1CV, Canada
Typefull-time
SenioritySenior
DepartmentEngineering
Company size10,000+ people
First seenOct 30, 2026 · 1w ago
Verified live15h ago
At a glanceSummarised by Seekless from the posting.
ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out
Highly accurate and detail-oriented
Strong communication and problem-solving skills
Help set design development direction and mentor other engineers
Strong understanding of Digital Design in RTL, Verilog HDL
Experience with synthesis, linting / CDC tools, equivalence checks
Knowledge of power saving techniques, including UPF/CPF based power-aware flows and checks
Experience with design flows, version control systems, integration and implementation of IPs to SoC
Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
Strong AI knowledge and experience in it's usage to develop skills and agents
Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
Excellent problem-solving and debugging skills
Bachelor's or Master's degree in Electrical Engineering / Computer Engineering
This role is not eligible for Visa sponsorship
Skills
RTL
Verilog HDL
synthesis
CDC tools
UPF
CPF
version control systems
Lint
CDC/RDC
LEC
STA
AI
DFT
DFD
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About the role
THE ROLE:
We are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.
Requirements
THE PERSON:
A successful candidate will have ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.
Responsibilities
KEY RESPONSIBILITIES:
•
Integration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC.
•
Synthesis, timing, lint and cdc closure to ensure high quality design.
•
Responsible to implement the design related to test, debug, clocks.
•
Understanding of low power design techniques and have good knowledge of the UPF based power-aware flow.
•
Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
•
Drive and hands-on flow development, automation, and scripting.
•
Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
•
Technical and schedule discussion with multi-site engineers and managers
Nice to have
PREFERRED EXPERIENCE:
•
Strong understanding of Digital Design in RTL, Verilog HDL
•
Experience with synthesis, linting / CDC tools, equivalence checks
•
Knowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.
•
Experience with design flows, version control systems, integration and
implementation of IPs to SoC.
•
Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
•
Strong AI knowledge and experience in it’s usage to develop skills and agents.
•
Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
•
Excellent problem-solving and debugging skills
ACADEMIC CREDENTIALS:
•
Bachelor’s or Master’s degree in Electrical Engineering / Computer Engineering preferred
Legal
This role is not eligible for Visa sponsorship.
Benefits
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
We are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.
THE PERSON:
A successful candidate will have ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.
KEY RESPONSIBILITIES:
•
Integration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC.
•
Synthesis, timing, lint and cdc closure to ensure high quality design.
•
Responsible to implement the design related to test, debug, clocks.
•
Understanding of low power design techniques and have good knowledge of the UPF based power-aware flow.
•
Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
•
Drive and hands-on flow development, automation, and scripting.
•
Work collaboratively across teams of IP designers, Physical Design team and SoC level leads.
•
Technical and schedule discussion with multi-site engineers and managers
PREFERRED EXPERIENCE:
•
Strong understanding of Digital Design in RTL, Verilog HDL
•
Experience with synthesis, linting / CDC tools, equivalence checks
•
Knowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.
•
Experience with design flows, version control systems, integration and
implementation of IPs to SoC.
•
Proficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA
•
Strong AI knowledge and experience in it’s usage to develop skills and agents.
•
Familiarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)
•
Excellent problem-solving and debugging skills
ACADEMIC CREDENTIALS:
•
Bachelor’s or Master’s degree in Electrical Engineering / Computer Engineering preferred
This role is not eligible for Visa sponsorship.