Emulation Verification Engineer
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Before you apply
LocationCupertino, California, United States; San Diego, California, United States; Sunnyvale, California, United States
Work modeon-site
Typefull-time
SenioritySenior
Experience10+ yrs
DepartmentHardware
Company size10,000+ people
PostedApr 9, 2026 · 7mo ago
Verified live2d ago
May no longer be actively hiring
Posted by the company on Apr 9, 2026
At a glanceSummarised by Seekless from the posting.
Minimum of BS + 10 years relevant industry experience
Understanding of the tool flow from RTL to Emulation is a huge plus
Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
Proven design verification skills
Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
Experience with System Verilog verification environments including C/C++ DPI, UVM
Experience with writing and debugging test FW
Experience on any Scripting (Perl/Python/TCL)
Excellent analytical and debug skills
Experience in UVM Acceleration is plus
Skills
Verilog
System Verilog
UVM
Palladium
Veloce
Zebu
FPGA
Xilinx
Altera
C/C++
DPI
Perl
Python
TCL
SystemVerilog
About the company
Imagine what you’ll do at Apple! New insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what we could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
About the role
At Apple, we’re passionate about changing the world! We have a critical impact on getting high quality functional products to millions of customers quickly! We are looking for you to join our design verification team focusing on the creation, deployment, and support of sophisticated emulation environments. In this highly transparent role, you will be at the center of a chip design effort collaborating with Architecture, Design and SW teams!
Description
As a member of the Emulation verification team, we play a key role in using Emulation for verification of large SoCs. The overall work will involve porting the design onto the Palladium platform, followed by completing the detailed Emulation testplans.
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Collaborate closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform
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Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
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Prepare and complete the test plan and perform reviews with the multi-functional teams
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Perform low power testing on emulation platform
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Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM
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Develop random stimulus infrastructure by reusing existing UVM simulation constraints.
Minimum qualifications
•
Minimum of BS + 10 years relevant industry experience.
Preferred qualifications
•
Understanding of the tool flow from RTL to Emulation is a huge plus
•
Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
•
Proven design verification skills
•
Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
•
Experience with System Verilog verification environments including C/C++ DPI, UVM
•
Experience with writing and debugging test FW
•
Experience on any Scripting (Perl/Python/TCL)
•
Excellent analytical and debug skills
•
Experience in UVM Acceleration is plus
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