Find jobs
Pricing
Sign in
FIND JOBS
PRICING
SIGN IN
SIGN UP
← Back
CA
Cadence
Principal Design Engineer
Save
Tailor resume
Apply
Location
2 Locations
Type
full-time
Company size
10,000+ people
First seen
2w ago
Last seen
4d ago
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Requirements
•
BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
•
8+ years of Design Verification experience with SV/UVM
•
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
•
Design Verification experience verifying complex designs and leading projects from concept to verification closure.
•
Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Nice to have
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
We’re doing work that matters. Help us solve what others can’t.
More roles at Cadence
Program Manager II
Security Receptionist
Intern Digital Implementation
Processor Core Logic Design/Architect
AI Engineer, Ontologies & Knowledge Graphs
Seekless
Product
Find jobs
Companies
Pricing
Legal
Privacy
Terms
Cookies
© 2026 SEEKLESS, INC. ALL RIGHTS RESERVED.
BUILT WITH CARE