Senior Electrical Engineer - FPGA Firmware
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Before you apply
LocationStar Catcher HQ, Jacksonville, Florida, United States
Typefull-time
SenioritySenior
Experience10+ yrs
DepartmentEngineering
Company size51–200 people
PostedOct 8, 2026 · 3w ago
Verified live13h ago
At a glanceSummarised by Seekless from the posting.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
10+ years of professional experience designing and verifying FPGA gateware in VHDL or Verilog
Experience with FPGA/SoC design toolchains, including synthesis, place-and-route, and timing closure
Demonstrated experience implementing real-time control loops in reconfigurable logic
Thorough understanding of version control best practices and tools for tracking changes to an FPGA baseline
Experience evaluating radiation-tolerant FPGA/SoC platforms, including Microchip RTG4/RT PolarFire nonvolatile configuration and AMD XQR Kintex UltraScale/XQR Versal SRAM-based configuration
Understanding configuration-upset mitigation and scrubbing where applicable, plus separate risks in user memory, logic, processors, and transceivers
Experience implementing DSP or signal-processing in FPGA fabric
Familiarity with spacecraft communications protocols (CCSDS) such as AOS, EPP, TM/TC, SPP
Experience with formal verification or advanced simulation methodologies, including transaction-based models for block- and top-level FPGA simulation
Experience with high-speed serial interfaces (e.g., PCIe, SpaceWire, Ethernet), control interfaces (e.g., I2C, SPI, RS-232/422), and memory interfaces (e.g., DDR3/DDR4)
Experience with FPGA devices (e.g., AMD Kintex/Virtex UltraScale+, Microchip RTG4 or RT PolarFire) and processor-integrated SoCs (e.g., AMD Zynq UltraScale+ or XQR Versal), or equivalent platforms
Familiarity with backplane-based architecture (e.g., SpaceVPX, VPX) and board-to-FPGA interface constraints
Experience with NASA/DoD life cycle and technical reviews (e.g., SRR, PDR, CDR)
Experience mentoring engineers or establishing team-wide design standards
Ability to prioritize assignments and complete design/project goals with minimal oversight in a fast-paced environment
U.S. citizenship, lawful permanent resident status, or ability to obtain required authorizations from U.S. Department of State
Skills
VHDL
Verilog
FPGA
SoC
DSP
I2C
SPI
RS-232/422
Ethernet
PCIe
SpaceWire
DDR3
DDR4
CCSDS
Microchip RTG4
RT PolarFire
AMD XQR Kintex UltraScale
XQR Versal SRAM
AMD Zynq UltraScale+
XQR Versal
SpaceVPX
VPX
Benefits
Health insurance
Dental insurance
Vision insurance
401(k)
Life insurance
Paid parental leave
Power the future of Space at Star Catcher
Star Catcher is building the first energy grid in space to power the orbital economy.
Today’s spacecraft must generate all of their own power, which caps what they can do and how long they can operate. But what if they could “plug” into a grid, the way buildings do on Earth? Instead of cables and outlets, Star Catcher is building the technology to wirelessly beam energy to spacecraft’s existing solar panels when and where they need it.
Be an early member of a team building an entirely new energy infrastructure at scale to power the next frontier.
About the role
Star Catcher Industries, Inc., located in Jacksonville, Florida, has an opportunity for a Senior Electrical Engineer - FPGA Firmware to support the development of space-to-space power beaming spacecraft and the Star Catcher Network, its orbital power grid.
Key Responsibilities
•
Lead FPGA gateware architecture for real-time control loops, including beam-control servo logic for Pointing, Acquisition & Tracking (PAT), and co-own interfaces with digital hardware, embedded software, and systems leads.
•
Decompose and allocate system and board-level requirements to FPGA specifications, and architect solutions targeting FPGA/SoC platforms against those requirements.
•
Review product specifications and generate module-level block diagrams, flow diagrams, and design concepts for FPGA subsystems.
•
Drive timing closure, pipelining, and clock-domain crossing strategy for mission-critical designs.
•
Set partitioning strategy between hard processor subsystems and reconfigurable fabric on SoC platforms.
•
Lead full lifecycle development of VHDL or Verilog gateware, from architecture through simulation, integration, and test on the circuit card assembly.
•
Map FPGA simulation work products to system-level requirements and capabilities, using complex block- and top-level simulations to verify performance ahead of hardware integration.
•
Lead bench-level system integration of FPGA designs with hardware, firmware, and software.
•
Refine and enforce consistent firmware development processes and version control practices across FPGA designs.
•
Mentor firmware engineers and establish FPGA design/verification standards.
•
Select and qualify FPGA/SoC platforms and associated toolchains for high-reliability, space-flight applications.
•
Support qualification and production test efforts, including troubleshooting in the event of test failures.
Basic Qualifications
•
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
•
Experience: 10+ years of professional experience designing and verifying FPGA gateware in VHDL or Verilog.
•
Experience with FPGA/SoC design toolchains, including synthesis, place-and-route, and timing closure.
•
Demonstrated experience implementing real-time control loops in reconfigurable logic.
•
Thorough understanding of version control best practices and tools for tracking changes to an FPGA baseline.
Desired Skills
•
Experience evaluating radiation-tolerant FPGA/SoC platforms, including Microchip RTG4/RT PolarFire nonvolatile configuration and AMD XQR Kintex UltraScale/XQR Versal SRAM-based configuration. Understand configuration-upset mitigation and scrubbing where applicable, plus separate risks in user memory, logic, processors, and transceivers.
•
Experience implementing DSP or signal-processing in FPGA fabric.
•
Familiarity with spacecraft communications protocols (CCSDS) such as AOS, EPP, TM/TC, SPP.
•
Experience with formal verification or advanced simulation methodologies, including transaction-based models for block- and top-level FPGA simulation.
•
Experience with high-speed serial interfaces (e.g., PCIe, SpaceWire, Ethernet), control interfaces (e.g., I2C, SPI, RS-232/422), and memory interfaces (e.g., DDR3/DDR4).
•
Experience with FPGA devices (e.g., AMD Kintex/Virtex UltraScale+, Microchip RTG4 or RT PolarFire) and processor-integrated SoCs (e.g., AMD Zynq UltraScale+ or XQR Versal), or equivalent platforms.
•
Familiarity with backplane-based architecture (e.g., SpaceVPX, VPX) and board-to-FPGA interface constraints.
•
Experience with NASA/DoD life cycle and technical reviews (e.g., SRR, PDR, CDR).
•
Experience mentoring engineers or establishing team-wide design standards.
•
Ability to prioritize assignments and complete design/project goals with minimal oversight in a fast-paced environment.
Help us deploy and scale space infrastructure that will drive our utilization of space forward! We offer a highly competitive benefits package including access to comprehensive medical, dental, and vision coverage, 401(k) retirement plan, life insurance, and paid parental leave, in addition to other benefits.
Legal
Star Catcher is an Equal Opportunity Employer; employment with Star Catcher is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
All offers of employment at Star Catcher are contingent upon results of a thorough background check and your ability to provide proof of eligibility to work in the US.
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.