DFT Design Engineer
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Before you apply
LocationJerusalem, Israel; TLV
Work modeon-site
Typefull-time
SeniorityMid
Experience4+ yrs
Company size1,001–5,000 people
PostedOct 13, 2026 · 3w ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
Minimum Bachelor's degree in Electronics Engineering
At least 4 years of experience in DFT
Strong experience in Scan Architecture, Scan Insertion, and ATPG execution
Experience defining and implementing scan procedures
Good experience with Mixed-Signal IP DFT
Hands-on experience with MBIST implementation and MBIST validation
Experience in RTL design, DFT integration, verification, and supporting DFT activities at IP/SoC level
Eligibility for employment consideration without regard to race, color, religion, etc.
Skills
SCAN Architecture
Scan Insertion
ATPG
MBIST
RTL
DFT
Job Details:
Job Description:
About the role
Altera is seeking a skilled DFT Design Engineer to contribute to the design and implementation of Design-for-Test (DFT) solutions for complex integrated circuits, ensuring high test coverage and efficient manufacturing test.
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Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
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Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including SCAN, MBIST). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
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Optimizes logic to qualify the design to meet test-coverage, DPM, and test-time/vector-memory reduction goals as well as design integrity for physical implementation.
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Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
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Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block.
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Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Experiment in DFT for mix signal IP required.
Qualifications:
•
Minimum Bachelor’s degree in Electronics Engineering.
•
At least 4 years of experience in DFT.
•
Strong experience in Scan Architecture, Scan Insertion, and ATPG execution.
•
Experience defining and implementing scan procedures.
•
Good experience with Mixed-Signal IP DFT.
•
Hands-on experience with MBIST implementation and MBIST validation.
•
Experience in RTL design, DFT integration, verification, and supporting DFT activities at IP/SoC level.
Job Type:
Regular
Shift:
Shift 1 (Israel)
Primary Location:
Jerusalem, Israel
Additional Locations:
TLV
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.