Senior Analog Mixed-Signal IC Layout Engineer
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Before you apply
LocationSingapore City, Singapore
SenioritySenior
DepartmentAnalog Layout & Design (SGP_Analog Layout)
Company size1,001–5,000 people
PostedOct 13, 2026 · 3w ago
Verified live2h ago
At a glanceSummarised by Seekless from the posting.
Pursuing BS or MS in EE/CS or related fields
Hardware engineering background with an emphasis in VLSI or Computer Architecture
Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture
Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog
Familiarity with verification methodologies like UVM, functional coverage, assertions
Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++
Real-world design and/or verification in Verilog/System Verilog
Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes
Familiarity with Synopsys EDA tools
Skills
Verilog
System Verilog
UVM
Python
Perl
C/C++
Synopsys EDA tools
PCIe
DDR
HBM
Serdes
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the role
We are looking for a Analog / Mixed-Signal Layout Engineerto join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.
Basic qualifications:
•
Pursuing BS or MS in EE/CS or related fields.
•
Hardware engineering background with an emphasis in VLSI or Computer Architecture.
•
Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
Required experience:
•
Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
•
Familiarity with verification methodologies like UVM, functional coverage, assertions.
•
Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.
Preferred experience:
•
Real-world design and/or verification in Verilog/System Verilog.
•
Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
•
Familiarity with Synopsys EDA tools.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.