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Role Overview
Responsible for enabling Foundry PDK teams and Foundry Design Service teams to deploy signoff‑quality standard cell, IO, and memory libraries using Cadence Liberate Characterization Suite. This role focuses on library modeling methodology, characterization techfile development, and design‑ready reference flow enablement aligned with foundry signoff requirements.
Key Responsibilities – Foundry PDK Team Support
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Support foundry PDK teams in development, validation, and maintenance of Liberate characterization techfiles for standard cell, IO, and memory libraries.
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Collaborate with foundry teams to define SPICE corner, PVT, and RC assumptions used for library signoff.
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Enable generation of signoff‑quality Liberty models (NLDM / CCS / CCSP) aligned with foundry requirements.
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Support characterization of timing, power, leakage, noise, and SI effects for advanced nodes.
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Assist foundry PDK qualification and IP vendor enablement through library quality checks and debugging.
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Work with foundry modeling and signoff teams to ensure consistency between library models and downstream STA, power, and reliability analysis.
Key Responsibilities – Foundry Design Service Team Support
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Develop and maintain design reference flows for standard cell, IO, and memory libraries used by foundry design service teams.
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Support integration of Liberate libraries into design implementation and signoff flows.
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Provide guidance on library usage, corner selection, and modeling trade‑offs for large‑scale SoC projects.
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Support characterization model selection for pre‑layout, post‑layout, ECO, and signoff stages.
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Assist design service teams in debugging timing, power, SI, and convergence issues related to library quality.
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Enable reusable and standardized library handoff flows across multiple design service projects.
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