Principal Logic Design Engineer - UALink IP/Subsystem
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Before you apply
LocationBengaluru, Karnataka, India
Work modeon-site
Typefull-time
SeniorityLead
Experience10–15 yrs
DepartmentDesign Engineering CCE2
Company size1,001–5,000 people
PostedSep 17, 2026 · 1mo ago
Verified live12h ago
At a glanceSummarised by Seekless from the posting.
Strong experience in RTL and microarchitecture development
Experience with high-speed interconnects and/or coherent fabrics
Strong understanding of computer architecture, networking/interconnect concepts, and data movement
Proficiency in SystemVerilog/Verilog
Strong understanding of CDC, reset architecture, performance, and hardware design methodology
10–15 years of experience
Direct UALink experience
Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols
Experience in AI/accelerator or high-performance compute systems
Skills
SystemVerilog
Verilog
UALink
PCIe
CXL
CCIX
CHI
Ethernet
RTL
SoC/IP design
COSMOS
About the company
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Logic Design Engineer – UALink IP/Subsystem
Experience
10–15 years
Job Summary
We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.
Key Responsibilities
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Lead architecture and RTL development for UALink IP/subsystems.
•
Translate protocol and system requirements into scalable hardware architecture.
•
Design high-bandwidth, low-latency data paths and control logic.
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Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
•
Define interfaces between UALink and other SoC/interconnect components.
•
Develop and review SystemVerilog RTL.
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Drive design optimization for performance, power, area, and latency.
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Work closely with verification, physical design, SoC integration, and firmware teams.
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Review design specifications and contribute to architectural decisions.
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Debug complex simulation and integration issues.
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Provide technical leadership and mentorship.
Required Skills
•
Strong experience in RTL and microarchitecture development.
•
Experience with high-speed interconnects and/or coherent fabrics.
•
Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
•
Proficiency in SystemVerilog/Verilog.
•
Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Preferred
•
Direct UALink experience.
•
Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
•
Experience in AI/accelerator or high-performance compute systems.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.