Digital - Digital Design Engineer (title will reflect experience)
LocationBay Area, Vancouver or Toronto
Work modeon-site
Typefull-time
DepartmentEngineering
EquityIncluded
Company size11+ people
First seen5mo ago
Last seen2h ago
About the role
Join the leading chiplet startup! As an Eliyan digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architecture specifications and RTL design descriptions for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. MUST BE WILLING TO WORK ONSITE - M-F
Key Responsibilities
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Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G)
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Develop micro-architecture specifications and implement digital designs using SystemVerilog
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Ensure compliance with Ethernet standards (IEEE 802.3)
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Optimize designs for power, area, and performance
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Collaborate with verification engineers for IP verification
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Work closely with physical design team for physical implementation
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Participate in design reviews and ensure design quality
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Develop and maintain all IP design collaterals that include documentation, RTL, SDC constraints, power intent definition (UPF/CPF), LINT/CDC rule files and waivers
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Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
Qualifications
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Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
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5+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
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Strong expertise in RTL and Assertion coding with SystemVerilog
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Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist
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Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training
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Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement
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Experience integrating 3rd party mixed signal IPs
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Proven track record of being part of a start-up like environment
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Knowledge of DRAM Controllers/PHYs and HBM Memory a plus