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Eliyan

Websiteeliyan.com

Company size51–200 people

New open roles (30 days)0

Median listing age199 days

New roles and listing age count from when Seekless first saw each role, not the employer's posting date.

21 Open RolesLast checked 3d ago

Engineering — 21 roles

DFT Implementation Lead

Bay Areaon-sitefull-timeVerified 3d ago

Lead15+ yrsTessentTetraMaxGenusTempus

Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms

Bay Areaon-sitefull-timeVerified 3d ago

Lead15+ yrsJiraMS ProjectSmartsheetConfluence

Silicon Validation, Test & Characterization Engineer (title will reflect experience)

Bay Areaon-sitefull-timeVerified 3d ago

Mid3+ yrsPythonTCLPCIeCXL

DV - Director of Design Verification

Bay Areaon-sitefull-timeVerified 3d ago

Director15+ yrsSystemVerilogUVMVerilog-AMSSVAMS

Photonics IC Validation and Characterization Engineer (title will reflect experience)

Bay Areaon-sitefull-timeVerified 3d ago

Mid3+ yrsPythonCTLEFFEDFE

DV - Staff (+) Verification Engineer -  AMS modeling

Bay Area, Vancouver or Torontoon-sitefull-timeVerified 3d ago

Lead5+ yrsSystemVerilogUVMPythonPerl

Digital - ASIC Design Automation & Integration Engineer

Bay Area, Vancouver or Torontoon-sitefull-timeVerified 3d ago

Senior5+ yrsPythonTclshell scriptingGit

PD - Sr Staff - Physical Verification Lead | Signoff & DRC

Bay Areaon-sitefull-timeVerified 3d ago

Lead15+ yrsCalibreIC ValidatorPythonPerl

PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |

Bay Areaon-sitefull-timeVerified 3d ago

Lead15+ yrsPythonSynopsysCadenceSiemens

DV - Principal Digital Verification Engineer

Vancouver, BC OR Bay Area, CAon-sitefull-timeVerified 3d ago

Lead15+ yrsSystemVerilogUVMPythonPerl

CAD - Staff AMS CAD Engineer

Bay Areaon-sitefull-timeVerified 3d ago

Lead5+ yrsCadence Virtuoso Layout/SchematicADE AssemblerPegasusQuantus

Digital - Digital Design Engineer (title will reflect experience)

Bay Area, Vancouver or Torontoon-sitefull-timeVerified 3d ago

Senior5+ yrsSystemVerilogRTLSDCUPF

Digital - Principal Systems/DSP Engineer

Bay Areaon-sitefull-timeVerified 3d ago

Lead10+ yrsMATLABSimulinkCPython

DV - Staff Verification Engineer - Serdes

Bay Area, Vancouver or Torontoon-sitefull-timeVerified 3d ago

Lead7+ yrsSystemVerilogUVMJasper Goldvc-formal

Digital - SerDes Digital Design Lead

Bay Areaon-sitefull-timeVerified 3d ago

Lead12+ yrsSystemVerilogRTLDSPFFE

PD - Principal, Physical Design

Bay Areaon-sitefull-timeVerified 3d ago

Lead8–12 yrsRTLGDSIIsynthesisPnR

Architecture - I/O Architect

Bay Areaon-sitefull-timeVerified 3d ago

Lead8+ yrsPCIeUCIeUALinkEthernet

Digital - Staff Digital Design Engineer - PHY

Bay Area, Vancouver or Torontoon-sitefull-timeVerified 3d ago

Lead8+ yrsSystemVerilogRTLSynopsys DCSynopsys Fusion Compiler

PD - IP Lead – Sr Staff, Physical Design

Bay Areaon-sitefull-timeVerified 3d ago

LeadRTLGDSIIsynthesisplace-and-route

DV - Digital Verification Engineer (Senior levels - Staff +)

Vancouver, BC OR Bay Area, CAon-sitefull-timeVerified 3d ago

Lead6+ yrsSystemVerilogUVMEthernetIEEE 802.3

Package & SI/PI - Signal and Power Integrity Engineer

Vancouver, BC OR Bay Area, CAon-sitefull-timeVerified 3d ago

Senior5+ yrsHFSSQ3DSiwavePowerDC

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Program Manager jobs7,800+