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24 Open Roles
Last checked 1d ago
Engineering — 24 roles
DFT Implementation Lead
Bay Area
on-site
full-time
1d ago
Lead
15+ yrs
JTAG
scan
BIST
memory BIST
Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms
Bay Area
on-site
full-time
1d ago
Senior
15+ yrs
Jira
MS Project
Smartsheet
Confluence
Program Management - Principal TPM – Packaging, SI/PI & System Integration
Bay Area
on-site
full-time
1d ago
Lead
15+ yrs
Jira
MS Project
Confluence
Smartsheet
Silicon Validation, Test & Characterization Engineer (title will reflect experience)
Bay Area
on-site
full-time
1d ago
3+ yrs
Python
TCL
PCIe
CXL
Optical - Director, OE Development (DOD)
Bay Area
on-site
full-time
1d ago
Director
12+ yrs
DV - Director of Design Verification
Bay Area
on-site
full-time
1d ago
Director
15+ yrs
SystemVerilog
UVM
Verilog-AMS
SVAMS
Photonics IC Validation and Characterization Engineer (title will reflect experience)
Bay Area
on-site
full-time
1d ago
Mid
3+ yrs
Python
DV - Staff (+) Verification Engineer - AMS modeling
Bay Area, Vancouver or Toronto
on-site
full-time
1d ago
Senior
5+ yrs
SystemVerilog
UVM
Jasper Gold
vc-formal
Digital - RTL Design Quality & Automation Engineer
Bay Area, Vancouver or Toronto
on-site
full-time
1d ago
3+ yrs
SystemVerilog
Python
Tcl
Git
PD - Sr Staff - Physical Verification Lead | Signoff & DRC
Bay Area
on-site
full-time
1d ago
Senior
15+ yrs
Python
Perl
Tcl
Calibre
PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |
Bay Area
on-site
full-time
1d ago
Senior
15+ yrs
Synopsys
Cadence
Siemens
UPF/CPF
DV - Principal Digital Verification Engineer
Vancouver, BC OR Bay Area, CA
on-site
full-time
1d ago
Senior
15+ yrs
SystemVerilog
UVM
Scripting languages
CAD - Staff AMS CAD Engineer
Bay Area
on-site
full-time
1d ago
Senior
5+ yrs
Cadence Virtuoso
ADE Assembler
Pegasus
Quantus
Digital - Digital Design Engineer (title will reflect experience)
Bay Area, Vancouver or Toronto
on-site
full-time
1d ago
Senior
5+ yrs
SystemVerilog
Ethernet
PCS
PMA
Digital - Principal Systems/DSP Engineer
Bay Area
on-site
full-time
1d ago
Senior
10+ yrs
MATLAB
Simulink
C
Python
DV - Staff Verification Engineer - Serdes
Bay Area, Vancouver or Toronto
on-site
full-time
1d ago
Senior
7+ yrs
UVM
SystemVerilog
SerDes
PCIePHY
Digital - SerDes Digital Design Lead
Bay Area
on-site
full-time
1d ago
Senior
12+ yrs
SystemVerilog
RTL
SerDes
DSP
PD - Principal, Physical Design
Bay Area
on-site
full-time
1d ago
Senior
8–12 yrs
ASIC
RTL-to-GDSII
synthesis
place-and-route
Architecture - I/O Architect
Bay Area
on-site
full-time
1d ago
Senior
8+ yrs
PCIe
UCIe
UALink
Ethernet
Digital - Staff Digital Design Engineer - PHY
Bay Area, Vancouver or Toronto
on-site
full-time
1d ago
Senior
SystemVerilog
Synopsys DC
Fusion Compiler
Cadence Genus
Package & SI/PI - Senior/Staff Packaging Engineer - Electro-Thermal
Bay Area
on-site
full-time
1d ago
Senior
ANSYS RedHawk-SC
RHSC-ET
SIwave
Cadence Sigrity
PD - IP Lead – Sr Staff, Physical Design
Bay Area
on-site
full-time
1d ago
Senior
RTL
GDSII
synthesis
place-and-route
DV - Digital Verification Engineer (Senior levels - Staff +)
Vancouver, BC OR Bay Area, CA
on-site
full-time
1d ago
Senior
6+ yrs
SystemVerilog
UVM
Ethernet
IEEE 802.3
Package & SI/PI - Signal and Power Integrity Engineer
Vancouver, BC OR Bay Area, CA
on-site
full-time
1d ago
Senior
5+ yrs
HFSS
Q3D
Siwave
PowerDC
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