Digital Design Verification Trainee
LocationMEX - Aguascalientes
SeniorityEntry
Company size1,001–5,000 people
PostedJul 6, 2026 · 3mo ago
Verified live17h ago
At a glanceSummarised by Seekless from the posting.
B.Sc. degree in Electrical or Computer Engineering
Basic knowledge in constrained random verification using UVM, OVM, AVM, or VMM methodologies
Basic knowledge and/or basic experience with object oriented languages; SystemVerilog is preferred
Experience with related programming/scripting languages (i.e. Python, TCL, Perl, C)
Knowledge of PC and Unix/Linux operating systems
Basic Knowledge of digital verification methods
Strong analytical and problem solving skills
Excellent verbal and written communication skills
Ability to work independently and in a team environment
Excellent interpersonal and team skills
Self-motivated and creative
Well organized, thorough, and detail oriented
Ability to multitask and prioritize multiple simultaneous responsibilities
Skills
UVM
OVM
AVM
VMM
SystemVerilog
Python
TCL
Perl
C
PC
Unix
Linux
Job Summary:
Semtech’s Signal Integrity Product Business Unit delivers high performance Signal Integrity IC’s for data communications and video broadcast industries. This role offers a rare opportunity to join a highly integrated and very collaborative group of digital, analog, and physical designers, to deliver highly integrated mixed signal IC’s.
As a key member of our Digital Design group, you will be working in a team environment contributing to development of advanced digital subsystems within mixed signal ICs. This versatile position will provide exposure to all areas of digital silicon development including definition, design, verification and implementation. As a member of the verification group and project team, you will provide high quality work and be accountable for helping the team meet its project milestones and objectives.
This position requires someone with a high energy level, strong communication skills and ability to work well as a part of a skilled development team.
Responsibilities:
•
Functional verification of high-speed digital circuits using a constrained random verification methodology (50%)
•
Behavioral modeling of analog circuits and mixed level simulation of analog/digital circuits (10%)
•
Create product and technical documents (5%)
•
Prepare project plans and schedules (2%)
•
Provide technical guidance of verification tasks and resources within a project team (5%)
•
Work with analog engineers, firmware engineers, system engineers and marketing to ensure the design meets all customer and performance requirements (8%)
•
Work with Validation, Test and Product Engineers to support the validation and qualification of the end product (5%)
•
Provide leadership, guidance and mentoring to other Engineers (5%)
•
Continual improvement of design verification and productivity. Review and enhance verification methodology. (10%)
Minimum Qualifications:
•
A B.Sc. degree in Electrical or Computer Engineering and minimum
•
Basic knowledge in constrained random verification using UVM, OVM, AVM, or VMM methodologies.
•
Basic knowledge and/or basic experience with object oriented languages; SystemVerilog is preferred.
•
Experience with related programming/scripting languages (i.e. Python, TCL, Perl, C.)
•
Knowledge of PC and Unix/Linux operating systems.
•
Basic Knowledge of digital verification methods.
•
Strong analytical and problem solving skills.
•
Excellent verbal and written communication skills.
•
Ability to work independently and in a team environment.
•
Excellent interpersonal and team skills.
•
Self-motivated and creative.
•
Well organized, thorough, and detail oriented.
•
Ability to multitask and prioritize multiple simultaneous responsibilities.
Legal
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.