DV - Staff Verification Engineer - Serdes
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Before you apply
SalaryNo pay range posted
LocationBay Area, Vancouver or Toronto
Work modeon-site
Typefull-time
SeniorityLead
Experience7+ yrs
DepartmentEngineering
Company size51–200 people
PostedApr 8, 2026 · 7mo ago
Verified live13h ago
May no longer be actively hiring
Posted by the company on Apr 8, 202695% of this company's open roles have been listed for 90+ daysNo pay range listed, though California requires one
At a glanceSummarised by Seekless from the posting.
BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces
Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR
Strong expertise in UVM/SystemVerilog, test environment and assertion coding
Experience in verifying mixed signal IPs as well as integration of VIPs
10+ years with demonstrated verification technical leadership
Experience with Formal verification with Jasper Gold or vc-formal
Experience with GLS simulations
Python/Perl/Tcl scripting for design verification
Proficiency in 3rd party tools for regression management and coverage analysis
Skills
SystemVerilog
UVM
Jasper Gold
vc-formal
Python
Perl
Tcl
About the role
Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You’ll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F.
Key Responsibilities:
•
Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
•
Create and maintain SystemVerilog/UVM-based verification environments
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Write and debug SystemVerilog/UVM compliant test cases for block and chip level
•
Maintain regression environments
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Collaborate with design team to ensure design quality
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Develop, maintain, and track various test plan items and progress towards RTL freeze
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Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
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Integration of 3rd party VIPs and coordinate feature/bug tracking requests
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As a technical leader, mentor junior verification engineers
•
GLS simulation for functional verification and power calculations
Required Qualifications:
•
BS + 7 years of verification experience with 4+ years in PHY or high-speed interfaces
•
Deep verification expertise in SerDes/PCIePHY, TX/RX equalization, CDR
•
Strong expertise in UVM/SystemVerilog, test environment and assertion coding
•
Experience in verifying mixed signal IPs as well as integration of VIPs
Preferred Qualifications:
•
10+ years with demonstrated verification technical leadership
•
Experience with Formal verification with Jasper Gold or vc-formal
•
Experience with GLS simulations
•
Python/Perl/Tcl scripting for design verification
•
Proficiency in 3rd party tools for regression management and coverage analysis
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