Advanced Package Development Engineer
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Before you apply
LocationCalifornia, United States
Typefull-time
SenioritySenior
Experience10+ yrs
DepartmentHardware
Company size10,000+ people
PostedNov 2, 2026 · 1d ago
Verified live1d ago
At a glanceSummarised by Seekless from the posting.
BS and 10+ years of experience in relevant industry experience
MS/PhD and 6+ years of relevant industry experience in advanced wafer-level packaging
Deep technical expertise in advanced packaging architectures and foundry processes
Hands-on experience reviewing GDS/layout data, physical verification (DRC/LVS), and working with IC layout/viewing tools (e.g., Calibre, Virtuoso, KLayout)
Proven track record managing foundry partners, defining DOEs, driving NPI engineering builds, and analyzing inline/end-of-line metrology and electrical test data
Solid background in packaging physics, multi-domain interactions (thermo-mechanical, warpage, thin-wafer handling, reliability, and SI/PI fundamentals)
Strong problem-solving, analytical rigor, and communication skills to interface effectively with cross-functional and overseas foundry/OSAT partners
Skills
GDSII/OASIS
DRC/LVS
Calibre
Virtuoso
KLayout
AI/ML
About the role
Join the team behind the technology in a billion pockets worldwide. Apple’s Advanced Packaging Program is seeking engineers to drive package integration and technology development for next-generation products.
In this role, you’ll contribute to the advanced packaging technologies that enable Apple’s industry-leading silicon performance. You’ll work alongside world-class engineers to solve complex integration challenges and bring new packaging innovations from concept to mass production.
Description
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You will be responsible for advanced packaging development and pathfinding.
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Drive engagement with leading-edge foundries/OSATs to lead package integration, process definition, and architecture efforts.
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Define specs, drive process windows, and establish advanced packaging solutions (2.5D/3D, hybrid bonding, high-density wafer-level interconnects).
Responsibilities
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Collaborate with cross-functional domains through the package architecture and definition process to deliver optimized solutions meeting electrical, mechanical, and thermal requirements.
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Drive process definition, baseline flow development, and margin validation in close collaboration with foundry/OSAT partners.
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Lead test vehicle (TV) definition, floorplanning, tapeout execution, and DOE build plans with foundries through development and NPI phases.
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Perform layout and GDS/mask review (GDSII/OASIS), ensuring DRC/LVS compliance and design-for-manufacturing (DFM) alignment with foundry design rules.
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Lead comprehensive data collection, statistical data analysis, and yield tracking across wafer-level process steps to drive yield enhancement and process centering.
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Drive failure analysis (FA), root-cause investigations, and issue resolution for wafer-level process excursions, defectivity, and reliability marginalities.
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Apply advanced data analytics and AI/ML techniques to convert complex foundry inline/metrology datasets into actionable process optimization insights.
Minimum qualifications
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BS and 10+ years of experience in relevant industry experience.
Preferred qualifications
•
MS/PhD and 6+ years of relevant industry experience in advanced wafer-level packaging.
•
Deep technical expertise in advanced packaging architectures and foundry processes
•
Hands-on experience reviewing GDS/layout data, physical verification (DRC/LVS), and working with IC layout/viewing tools (e.g., Calibre, Virtuoso, KLayout).
•
Proven track record managing foundry partners, defining DOEs, driving NPI engineering builds, and analyzing inline/end-of-line metrology and electrical test data.
•
Solid background in packaging physics, multi-domain interactions (thermo-mechanical, warpage, thin-wafer handling, reliability, and SI/PI fundamentals).
•
Strong problem-solving, analytical rigor, and communication skills to interface effectively with cross-functional and overseas foundry/OSAT partners.
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